UB Paderborn / Katalog / Suche / in CDI

BER Testing of Communication Interfaces

IEEE transactions on instrumentation and measurement, 2008-05, Vol.57 (5), p.897-906

2008

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IEEE_Xplore

A Laboratory Setup and Teaching Methodology for Wireless and Mobile Embedded Systems

IEEE transactions on education, 2008-08, Vol.51 (3), p.378-384

2008

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IEEE_Xplore

GALDS: a complete framework for designing multiclock ASICs and SoCs

IEEE transactions on very large scale integration (VLSI) systems, 2005-06, Vol.13 (6), p.641-654

2005

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IEEE_Xplore

Arithmetic transforms for compositions of sequential and imprecise datapaths

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-07, Vol.25 (7), p.1382-1391

2006

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IEEE_Xplore

Generalized mechanics and dynamics of metal cutting operations for unified simulations

International journal of machine tools & manufacture, 2016-05, Vol.104, p.1-13

2016

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Verfügbarkeit prüfen

Design verification by test vectors and arithmetic transform universal test set

IEEE transactions on computers, 2004-05, Vol.53 (5), p.628-640

2004

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IEEE_Xplore

Generalized modelling of cutting tool geometries for unified process simulation

International journal of machine tools & manufacture, 2016-05, Vol.104, p.14-25

2016

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Verfügbarkeit prüfen

Incorporating efficient assertion checkers into hardware emulation

2005 International Conference on Computer Design, 2005, p.221-228

2005

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IEEE_Xplore

Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-03, Vol.31 (3), p.343-355

2012

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IEEE_Xplore

Debug enhancements in assertion-checker generation

IET computers & digital techniques, 2007-11, Vol.1 (6), p.669-677

2007

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Verfügbarkeit prüfen

A deterministic multivariate interpolation algorithm for small finite fields

IEEE transactions on computers, 2002-09, Vol.51 (9), p.1100-1105

2002

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IEEE_Xplore

Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks

IEEE transactions on very large scale integration (VLSI) systems, 2012-03, Vol.20 (3), p.523-536

2012

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IEEE_Xplore

FPGA emulation of quantum circuits

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings, 2004, p.310-315

2004

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IEEE_Xplore

Architectures of increased availability wireless sensor network nodes

2004 International Conferce on Test, 2004, p.1232-1241

2004

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IEEE_Xplore

A Fault Tolerant Hierarchical Network on Chip Router Architecture

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011, p.445-453

2011

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IEEE_Xplore

The role of super-fast transforms in speeding up quantum computations

Proceedings - International Symposium on Multiple-Valued Logic, 2002, p.129-135

2002

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IEEE_Xplore

Designing and Using FPGAs beyond Classical Binary Logic: Opportunities in Nano-Scale Integration Age

2009 39th International Symposium on Multiple-Valued Logic, 2009, p.268-273

Zilic, Z.

2009

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IEEE_Xplore

Debug Aware AXI-based Network Interface

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011, p.399-407

2011

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IEEE_Xplore

Design and implementation of error detection and correction circuitry for multilevel memory protection

Proceedings - International Symposium on Multiple-Valued Logic, 2002, p.89-95

2002

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IEEE_Xplore

Using decision diagrams to design ULMs for FPGAs

IEEE transactions on computers, 1998-09, Vol.47 (9), p.971-982

1998

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IEEE_Xplore

A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing

First International Symposium on Networks-on-Chip (NOCS'07), 2007, p.195-204

2007

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IEEE_Xplore

Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-09, Vol.29 (9), p.1436-1448

2010

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IEEE_Xplore

A multiple-valued Reed-Muller transform for incompletely specified functions

IEEE transactions on computers, 1995-08, Vol.44 (8), p.1012-1020

1995

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IEEE_Xplore

Arithmetic transforms for verifying compositions of sequential datapaths

Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001, 2001, p.348-353

2001

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IEEE_Xplore

A distributed AXI-based platform for post-silicon validation

29th VLSI Test Symposium, 2011, p.8-13

2011

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IEEE_Xplore

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BER Testing of Communication Interfaces

A Laboratory Setup and Teaching Methodology for Wireless and Mobile Embedded Systems

GALDS: a complete framework for designing multiclock ASICs and SoCs

Arithmetic transforms for compositions of sequential and imprecise datapaths

Generalized mechanics and dynamics of metal cutting operations for unified simulations

Design verification by test vectors and arithmetic transform universal test set

Generalized modelling of cutting tool geometries for unified process simulation

Incorporating efficient assertion checkers into hardware emulation

Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems

Debug enhancements in assertion-checker generation

A deterministic multivariate interpolation algorithm for small finite fields

Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks

FPGA emulation of quantum circuits

Architectures of increased availability wireless sensor network nodes

A Fault Tolerant Hierarchical Network on Chip Router Architecture

The role of super-fast transforms in speeding up quantum computations

Designing and Using FPGAs beyond Classical Binary Logic: Opportunities in Nano-Scale Integration Age

Debug Aware AXI-based Network Interface

Design and implementation of error detection and correction circuitry for multilevel memory protection

Using decision diagrams to design ULMs for FPGAs

A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing

Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers

A multiple-valued Reed-Muller transform for incompletely specified functions

Arithmetic transforms for verifying compositions of sequential datapaths

A distributed AXI-based platform for post-silicon validation

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