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Low-Blind-Period Differential Sampler for High-Speed Serial Link Receivers

IEEE transactions on circuits and systems. II, Express briefs, 2011-08, Vol.58 (8), p.497-501

Zhuang, Jingcheng

2011

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IEEE_Xplore

Design of Spur-Free \Sigma\Delta Frequency Tuning Interface for Digitally Controlled Oscillators

IEEE transactions on circuits and systems. II, Express briefs, 2015-01, Vol.62 (1), p.46-50

2015

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IEEE_Xplore

A Technique to Reduce Phase/Frequency Modulation Bandwidth in a Polar RF Transmitter

IEEE transactions on circuits and systems. I, Regular papers, 2010-08, Vol.57 (8), p.2196-2207

2010

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IEEE_Xplore

Linear Equalization and PVT-Independent DC Wander Compensation for AC-Coupled PCIe 3.0 Receiver Front End

IEEE transactions on circuits and systems. II, Express briefs, 2011-05, Vol.58 (5), p.289-293

2011

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IEEE_Xplore

A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2006-11, Vol.53 (11), p.1205-1209

2006

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IEEE_Xplore

A Low-Power, Fast Acquisition, Data Recovery Circuit With Digital Threshold Decision for SFI-5 Application

IEEE transactions on very large scale integration (VLSI) systems, 2009-12, Vol.17 (12), p.1742-1748

2009

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IEEE_Xplore

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

IPSJ Transactions on System LSI Design Methodology, 2014, Vol.7, pp.2-15

2014

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A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS

2007 IEEE Custom Integrated Circuits Conference, 2007, p.543-546

2007

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IEEE_Xplore

A Gigahertz Cyclic Injection DLL Clock Generator with an Infinite Acquisition Range

2006 49th IEEE International Midwest Symposium on Circuits and Systems, 2006, Vol.2, p.16-19

2006

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IEEE_Xplore

Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL

2013 European Conference on Circuit Theory and Design (ECCTD), 2013, p.1-4

2013

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A low-power all-digital PLL architecture based on phase prediction

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012, p.797-800

2012

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IEEE_Xplore

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Information and Media Technologies, 2014, Vol.9(1), pp.1-14

2014

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A 3.3 GHz LC-based digitally controlled oscillator with 5kHz frequency resolution

2007 IEEE Asian Solid-State Circuits Conference, 2007, p.428-431

2007

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IEEE_Xplore

Computationally efficient, event-driven simulation of wireless transmitters using a noisy local oscillator

2009 IEEE Dallas Circuits and Systems Workshop (DCAS), 2009, p.1-4

2009

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IEEE_Xplore

A low complexity digital phase-locked loop based frequency synthesizer

Zhuang, Jingcheng

2008

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Reduced in-lock error DLL-based clock synthesiser with novel charge pump phase comparator

Electronics letters, 2003-01, Vol.39 (1), p.1-1

2003

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A 2.5 Gb/s, Low Power Clock and Data Recovery Circuit

2007 Canadian Conference on Electrical and Computer Engineering, 2007, p.526-529

2007

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IEEE_Xplore

A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System

2006 IEEE International SOC Conference, 2006, p.123-126

2006

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IEEE_Xplore

A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider

2006 Canadian Conference on Electrical and Computer Engineering, 2006, p.701-704

2006

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IEEE_Xplore

An eye detection technique for clock and data recovery applications

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.-5162

2006

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IEEE_Xplore

Noise, spur characteristics and in-lock error reduction of DLL-based frequency synthesizers

2004 International Conference on Communications, Circuits and Systems (IEEE Cat. No.04EX914), 2004, Vol.2, p.1443-1446 Vol.2

2004

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IEEE_Xplore

Reduced in-lock error DLL-based clock synthesiser with novel charge pump phase comparator

Electronics letters, 2003-01, Vol.39 (1), p.48

2003

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Verfügbarkeit prüfen

Low spur content DLL-based frequency synthesizer design

Zhuang, Jingcheng

2004

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A delay-locked frequency synthesizer with low phase noise performance

2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668), 2003, p.461-464

2003

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IEEE_Xplore

Amulti-level phase/frequency detector for clock and data recoveryapplications

Canadian Conference on Electrical and Computer Engineering, 2005, 2005, p.828-830

2005

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IEEE_Xplore

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Low-Blind-Period Differential Sampler for High-Speed Serial Link Receivers

Design of Spur-Free \Sigma\Delta Frequency Tuning Interface for Digitally Controlled Oscillators

A Technique to Reduce Phase/Frequency Modulation Bandwidth in a Polar RF Transmitter

Linear Equalization and PVT-Independent DC Wander Compensation for AC-Coupled PCIe 3.0 Receiver Front End

A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction

A Low-Power, Fast Acquisition, Data Recovery Circuit With Digital Threshold Decision for SFI-5 Application

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS

A Gigahertz Cyclic Injection DLL Clock Generator with an Infinite Acquisition Range

Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL

A low-power all-digital PLL architecture based on phase prediction

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

A 3.3 GHz LC-based digitally controlled oscillator with 5kHz frequency resolution

Computationally efficient, event-driven simulation of wireless transmitters using a noisy local oscillator

A low complexity digital phase-locked loop based frequency synthesizer

Reduced in-lock error DLL-based clock synthesiser with novel charge pump phase comparator

A 2.5 Gb/s, Low Power Clock and Data Recovery Circuit

A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System

A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider

An eye detection technique for clock and data recovery applications

Noise, spur characteristics and in-lock error reduction of DLL-based frequency synthesizers

Reduced in-lock error DLL-based clock synthesiser with novel charge pump phase comparator

Low spur content DLL-based frequency synthesizer design

A delay-locked frequency synthesizer with low phase noise performance

Amulti-level phase/frequency detector for clock and data recoveryapplications

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