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(0 0 l)-oriented Bi 2Sr 2Co 2O y and Ca 3Co 4O 9 films: Self-assembly orientation and growth mechanism by chemical solution deposition

Acta materialia, 2010, Vol.58 (12), p.4281-4291

2010

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A 0.002-mm2, 2.9-μW Pulse-Frequency-Modulation based Temperature Sensor with 40-mK Resolution

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-4

2024

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A 0.0021 mm 2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS

IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.8-20

2017

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A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS

IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.8-20

2017

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A 0.0043-mm 2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R- RC Network

IEEE transactions on very large scale integration (VLSI) systems, 2023-08, Vol.31 (8), p.1248-1252

2023

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A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network

IEEE transactions on very large scale integration (VLSI) systems, 2023-08, Vol.31 (8), p.1248-1252

2023

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A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages

2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2016, p.145-148

2016

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A 0.012mm2 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply

2023 IEEE Custom Integrated Circuits Conference (CICC), 2023, p.1-2

2023

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A 0.016 mm 2 0.26-$\mu$ W/MHz 60–240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

IEEE journal of solid-state circuits, 2019-08, Vol.54 (8), p.2186-2194

2019

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A 0.016 mm2 0.26-[Formula Omitted]W/MHz 60–240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

IEEE journal of solid-state circuits, 2019-01, Vol.54 (8), p.2186

2019

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A 0.016 mm2 0.26- \mu W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

IEEE journal of solid-state circuits, 2019-08, Vol.54 (8), p.2186-2194

2019

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A 0.016mm 2 Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling

IEEE transactions on circuits and systems. II, Express briefs, 2023-10, Vol.70 (10), p.3792-3796

2023

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A 0.016mm2 Active Area 4GHz Fully Ring-Oscillator-based Cascaded Fractional-N PLL with Burst-Mode Sampling

IEEE transactions on circuits and systems. II, Express briefs, 2023-10, Vol.70 (10), p.1-1

2023

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A 0.02% THD and 80 dB PSRR filterless class D amplifier with direct lithium battery hookup in mobile application

半导体学报：英文版, 2017, Vol.38 (7), p.56-63

Hao Zheng Zhangming Zhu Rui Ma

2017

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A 0.02% THD and 80 dB PSRR filterless class D amplifier with direct lithium battery hookup in mobile application

Journal of semiconductors, 2017-07, Vol.38 (7), p.60-67

2017

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A 0.02% THD and 80 dB PSRR filterless class D amplifier with direct lithium battery hookup in mobile application Project supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044)

Journal of semiconductors, 2017-07, Vol.38 (7)

2017

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A 0.04% BER Strong PUF With Cell-Bias-Based CRPs Filtering and Background Offset Calibration

IEEE transactions on circuits and systems. I, Regular papers, 2020-11, Vol.67 (11), p.3853-3865

2020

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A 0.048ns/°C delay generator with variation self-calibration structure(VSCS) for HVICs

2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2016, p.480-483

2016

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A $$0.058\,\hbox {mm}^2\,\,24\,\upmu \hbox {W}$$ 0.058 mm 2 24 μ W Temperature Sensor in $$40\,\hbox {nm}$$ 40 nm CMOS Process with $${\pm }\,0.5\,^{\circ }\hbox {C}$$ ± 0.5 ∘ C Inaccuracy from − 55 to $$175\,^{\circ }\hbox {C}$$ 175 ∘ C

Circuits, systems, and signal processing, 2018-06, Vol.37 (6), p.2278-2298

2018

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A 0.058 mm 2 24 μ W Temperature Sensor in 40 nm CMOS Process with ± 0.5 ∘ C Inaccuracy from − 55 to 175 ∘ C

Circuits, systems, and signal processing, 2018-06, Vol.37 (6), p.2278-2298

2018

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A 0.058mm224μW Temperature Sensor in 40nm CMOS Process with ±0.5∘C Inaccuracy from − 55 to 175∘C

Circuits, systems, and signal processing, 2018, Vol.37 (6), p.2278-2298

2018

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A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

2010 Symposium on VLSI Technology, 2010, p.19-20

2010

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A 0.073-mm2 10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM

2015 IEEE Custom Integrated Circuits Conference (CICC), 2015, p.1-4

2015

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A 0.08%/V 32.3-ppm/ ^ C 36.6-kHz Unregulated Current-Reuse Ring Oscillator With V} -Ratio-Based Compensation Using One-Type-Only Resistor

IEEE journal of solid-state circuits, 2024-04, p.1-13

2024

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A 0.1-1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process

Journal of semiconductors, 2016-05, Vol.37 (5), p.90-96

钟波朱樟明

2016

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(0 0 l)-oriented Bi 2Sr 2Co 2O y and Ca 3Co 4O 9 films: Self-assembly orientation and growth mechanism by chemical solution deposition

A 0.002-mm2, 2.9-μW Pulse-Frequency-Modulation based Temperature Sensor with 40-mK Resolution

A 0.0021 mm 2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS

A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS

A 0.0043-mm 2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R- RC Network

A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network

A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages

A 0.012mm2 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply

A 0.016 mm 2 0.26-$\mu$ W/MHz 60–240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

A 0.016 mm2 0.26-[Formula Omitted]W/MHz 60–240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

A 0.016 mm2 0.26- \mu W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

A 0.016mm 2 Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling

A 0.016mm2 Active Area 4GHz Fully Ring-Oscillator-based Cascaded Fractional-N PLL with Burst-Mode Sampling

A 0.02% THD and 80 dB PSRR filterless class D amplifier with direct lithium battery hookup in mobile application

A 0.02% THD and 80 dB PSRR filterless class D amplifier with direct lithium battery hookup in mobile application

A 0.02% THD and 80 dB PSRR filterless class D amplifier with direct lithium battery hookup in mobile application Project supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044)

A 0.04% BER Strong PUF With Cell-Bias-Based CRPs Filtering and Background Offset Calibration

A 0.048ns/°C delay generator with variation self-calibration structure(VSCS) for HVICs

A $$0.058\,\hbox {mm}^2\,\,24\,\upmu \hbox {W}$$ 0.058 mm 2 24 μ W Temperature Sensor in $$40\,\hbox {nm}$$ 40 nm CMOS Process with $${\pm }\,0.5\,^{\circ }\hbox {C}$$ ± 0.5 ∘ C Inaccuracy from − 55 to $$175\,^{\circ }\hbox {C}$$ 175 ∘ C

A 0.058 mm 2 24 μ W Temperature Sensor in 40 nm CMOS Process with ± 0.5 ∘ C Inaccuracy from − 55 to 175 ∘ C

A 0.058mm224μW Temperature Sensor in 40nm CMOS Process with ±0.5∘C Inaccuracy from − 55 to 175∘C

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

A 0.073-mm2 10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM

A 0.08%/V 32.3-ppm/ ^ C 36.6-kHz Unregulated Current-Reuse Ring Oscillator With V} -Ratio-Based Compensation Using One-Type-Only Resistor

A 0.1-1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process

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