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A fully integrated reprogrammable memristor–CMOS system for efficient multiply–accumulate operations

Nature electronics, 2019-07, Vol.2 (7), p.290-299

2019

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A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding

IEEE journal of solid-state circuits, 2015-04, Vol.50 (4), p.1070-1079

2015

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SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference

IEEE journal of solid-state circuits, 2021-02, Vol.56 (2), p.636-647

2021

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Predicting error floors of structured LDPC codes: deterministic bounds and estimates

IEEE journal on selected areas in communications, 2009-08, Vol.27 (6), p.908-917

2009

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Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM

IEEE journal of solid-state circuits, 2014-03, Vol.49 (3), p.783-794

2014

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Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices

IEEE transactions on communications, 2009-11, Vol.57 (11), p.3258-3268

2009

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A Native Stochastic Computing Architecture Enabled by Memristors

IEEE transactions on nanotechnology, 2014-03, Vol.13 (2), p.283-293

2014

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Designing Practical Polar Codes Using Simulation-Based Bit Selection

IEEE journal on emerging and selected topics in circuits and systems, 2017-12, Vol.7 (4), p.594-603

2017

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An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring

IEEE journal of solid-state circuits, 2015-01, Vol.50 (1), p.375-390

2015

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Analysis of Absorbing Sets and Fully Absorbing Sets of Array-Based LDPC Codes

IEEE transactions on information theory, 2010-01, Vol.56 (1), p.181-201

2010

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A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating

IEEE journal of solid-state circuits, 2015-02, Vol.50 (2), p.464-475

2015

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HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021, p.845-856

2021

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An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.843-855

2010

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Characterization of Heavy-Ion-Induced Single-Event Effects in 65 nm Bulk CMOS ASIC Test Chips

IEEE transactions on nuclear science, 2014-10, Vol.61 (5), p.2694-2701

2014

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Visualization of micro-agents and surroundings by real-time multicolor fluorescence microscopy

Scientific reports, 2022-08, Vol.12 (1), p.13375-13375, Article 13375

2022

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Association between serum branched chain amino acids, mammalian target of rapamycin levels and the risk of gestational diabetes mellitus: a 1:1 matched case control study

BMC pregnancy and childbirth, 2024-10, Vol.24 (1), p.633-10, Article 633

2024

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Optimization of Grinding Parameters for the Workpiece Surface and Material Removal Rate in the Belt Grinding Process for Polishing and Deburring of 45 Steel

Applied sciences, 2020-09, Vol.10 (18), p.6314

2020

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An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS

IEEE journal of solid-state circuits, 2014-05, Vol.49 (5), p.1271-1284

2014

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Efficient Hardware Architecture for Sparse Coding

IEEE transactions on signal processing, 2014-08, Vol.62 (16), p.4173-4186

2014

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A 1920 \times 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles

IEEE journal of solid-state circuits, 2018-01, Vol.53 (1), p.76-90

2018

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A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.224-226

2018

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Forward-Projection Architecture for Fast Iterative Image Reconstruction in X-Ray CT

IEEE transactions on signal processing, 2012-10, Vol.60 (10), p.5508-5518

2012

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Error patterns in belief propagation decoding of polar codes and their mitigation methods

2016 50th Asilomar Conference on Signals, Systems and Computers, 2016, p.1199-1203

2016

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Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems

IEEE transactions on circuits and systems. II, Express briefs, 2012-12, Vol.59 (12), p.952-956

2012

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Design and Evaluation of Confidence-Driven Error-Resilient Systems

IEEE transactions on very large scale integration (VLSI) systems, 2014-08, Vol.22 (8), p.1727-1737

2014

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A fully integrated reprogrammable memristor–CMOS system for efficient multiply–accumulate operations

A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding

SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference

Predicting error floors of structured LDPC codes: deterministic bounds and estimates

Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM

Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices

A Native Stochastic Computing Architecture Enabled by Memristors

Designing Practical Polar Codes Using Simulation-Based Bit Selection

An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring

Analysis of Absorbing Sets and Fully Absorbing Sets of Array-Based LDPC Codes

A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating

HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer

An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors

Characterization of Heavy-Ion-Induced Single-Event Effects in 65 nm Bulk CMOS ASIC Test Chips

Visualization of micro-agents and surroundings by real-time multicolor fluorescence microscopy

Association between serum branched chain amino acids, mammalian target of rapamycin levels and the risk of gestational diabetes mellitus: a 1:1 matched case control study

Optimization of Grinding Parameters for the Workpiece Surface and Material Removal Rate in the Belt Grinding Process for Polishing and Deburring of 45 Steel

An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS

Efficient Hardware Architecture for Sparse Coding

A 1920 \times 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles

A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI

Forward-Projection Architecture for Fast Iterative Image Reconstruction in X-Ray CT

Error patterns in belief propagation decoding of polar codes and their mitigation methods

Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems

Design and Evaluation of Confidence-Driven Error-Resilient Systems

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