UB Paderborn / Katalog / Suche / in CDI

1 – 25 von 146

Sortiert nach

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips

IEEE MICRO, 2018-03, Vol.38 (2), p.30-41

2018

Volltextzugriff (PDF)

Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-11, Vol.36 (11), p.1817-1830

2017

Volltextzugriff (PDF)

Area-efficient pipelining for FPGA-targeted high-level synthesis

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6

2015

Volltextzugriff (PDF)

Co-designing Model Compression Algorithms and Hardware Accelerators for Efficient Deep Learning

Zhao, Ritchie

2020

Volltextzugriff (PDF)

Building Efficient Deep Neural Networks With Unitary Group Convolutions

2019 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), 2019, p.11295-11304

2019

Volltextzugriff (PDF)

Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017, p.15-24

2017

Volltextzugriff (PDF)

Enabling adaptive loop pipelining in high-level synthesis

2017 51st Asilomar Conference on Signals, Systems, and Computers, 2017, p.131-135

2017

Volltextzugriff (PDF)

Binarized Convolutional Neural Networks with Separable Filters for Efficient Hardware Acceleration

2017 IEEE Conference on Computer Vision and Pattern Recognition Workshops (CVPRW), 2017, p.344-352

2017

Volltextzugriff (PDF)

With Shared Microexponents, A Little Shifting Goes a Long Way

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023, p.1-13

2023

Volltextzugriff (PDF)

Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL

IEEE solid-state circuits letters, 2019-12, Vol.2 (12), p.289-292

2019

Volltextzugriff (PDF)

Improving high-level synthesis with decoupled data structure optimization

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6

2016

Volltextzugriff (PDF)

Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018, p.269-278

2018

Volltextzugriff (PDF)

A Parallel Bandit-Based Approach for Autotuning FPGA Compilation

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017, p.157-166

2017

Volltextzugriff (PDF)

Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017, p.189-194

2017

Volltextzugriff (PDF)

ElasticFlow: A complexity-effective approach for pipelining irregular loop nests

2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015, p.78-85

2015

Volltextzugriff (PDF)

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS

2019 Symposium on VLSI Circuits, 2019, p.C30-C31

2019

Volltextzugriff (PDF)

ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015, p.78-85

2015

Volltextzugriff (PDF)

Dynamic material performance of cold-formed steel hollow sections： a state-of-the-art review

Frontiers of Structural and Civil Engineering, 2017-06, Vol.11 (2), p.209-227

2017

Volltextzugriff (PDF)

Mechanical properties of high-entropy alloys with emphasis on face-centered cubic alloys

Progress in materials science, 2019-05, Vol.102 (C), p.296-345

2019

Volltextzugriff (PDF)

On the damage tolerance of 3-D printed Mg-Ti interpenetrating-phase composites with bioinspired architectures

Nature communications, 2022-06, Vol.13 (1), p.3247-3247, Article 3247

2022

Volltextzugriff (PDF)

Cryoforged nanotwinned titanium with ultrahigh strength and ductility

Science (American Association for the Advancement of Science), 2021-09, Vol.373 (6561), p.1363-1368

2021

Volltextzugriff (PDF)

Short-range order and its impact on the CrCoNi medium-entropy alloy

Nature (London), 2020-05, Vol.581 (7808), p.283-287

2020

Volltextzugriff (PDF)

Ultra-strong tungsten refractory high-entropy alloy via stepwise controllable coherent nanoprecipitations

Nature communications, 2023-05, Vol.14 (1), p.3006-3006, Article 3006

2023

Volltextzugriff (PDF)

High Open‐Circuit Voltages in Tin‐Rich Low‐Bandgap Perovskite‐Based Planar Heterojunction Photovoltaics

Advanced materials (Weinheim), 2017-01, Vol.29 (2)

2017

Volltextzugriff (PDF)

1 – 25 von 146

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(125)
Mit Volltextzugriff
(124)

Publikationsform

Sprache

Erscheinungsjahr

n.n

Neu hinzugefügt

... seit 7 Tagen
(1)
... seit 30 Tagen
(2)

Menü

Weitere Dienste

Einstellungen

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips

Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests

Area-efficient pipelining for FPGA-targeted high-level synthesis

Serving DNNs in Real Time at Datacenter Scale with Project Brainwave

Co-designing Model Compression Algorithms and Hardware Accelerators for Efficient Deep Learning

Building Efficient Deep Neural Networks With Unitary Group Convolutions

Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs

Enabling adaptive loop pipelining in high-level synthesis

Binarized Convolutional Neural Networks with Separable Filters for Efficient Hardware Acceleration

With Shared Microexponents, A Little Shifting Goes a Long Way

Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL

Improving high-level synthesis with decoupled data structure optimization

Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs

A Parallel Bandit-Based Approach for Autotuning FPGA Compilation

Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis

ElasticFlow: A complexity-effective approach for pipelining irregular loop nests

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS

ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests

Dynamic material performance of cold-formed steel hollow sections： a state-of-the-art review

Mechanical properties of high-entropy alloys with emphasis on face-centered cubic alloys

On the damage tolerance of 3-D printed Mg-Ti interpenetrating-phase composites with bioinspired architectures

Cryoforged nanotwinned titanium with ultrahigh strength and ductility

Short-range order and its impact on the CrCoNi medium-entropy alloy

Ultra-strong tungsten refractory high-entropy alloy via stepwise controllable coherent nanoprecipitations

High Open‐Circuit Voltages in Tin‐Rich Low‐Bandgap Perovskite‐Based Planar Heterojunction Photovoltaics

Suchergebnisse filtern