UB Paderborn / Katalog / Suche / in CDI

Assessing Contact Graph Routing Performance and Reliability in Distributed Satellite Constellations

Journal of Computer Networks and Communications, 2017-01, Vol.2017 (2017), p.1-18

2017

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Combining a performance estimation methodology with a hardware/software codesign flow supporting multiprocessor systems

IEEE transactions on software engineering, 2002-09, Vol.28 (9), p.822-831

2002

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Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation

IEEE transactions on very large scale integration (VLSI) systems, 2006-04, Vol.14 (4), p.349-360

2006

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Assessing the Static and Dynamic Sensitivity of a Commercial Off-the-Shelf Multicore Processor for Noncritical Avionic Applications

Journal of nanotechnology, 2018-01, Vol.2018 (2018), p.1-8

2018

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A fault-tolerant deadlock-free adaptive routing for on chip interconnects

2011 Design, Automation & Test in Europe, 2011, p.1-4

2011

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Towards a tool for implementing delay-free ECC in embedded memories

2011 IEEE 29th International Conference on Computer Design (ICCD), 2011, p.441-442

2011

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Eliminating speed penalty in ECC protected memories

2011 Design, Automation & Test in Europe, 2011, p.1-6

2011

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An efficient architecture model for systematic design of application-specific multiprocessor SoC

Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, 2001, p.55-62

2001

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Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design

2003 Design, Automation and Test in Europe Conference and Exhibition, 2003, p.132-137 suppl.

2003

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Design for test and reliability in ultimate CMOS

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, p.677-682

2012

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Multi-level communication synthesis of heterogeneous multilanguage specification

Proceedings 2000 International Conference on Computer Design, 2000, p.525-530

2000

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Design space exploration for hardware/software codesign of multiprocessor systems

Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668), 2000, p.8-13

2000

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Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes

18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07), 2007, p.195-201

2007

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Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs

2017 18th IEEE Latin American Test Symposium (LATS), 2017, p.1-4

2017

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Evidences of stochastic Bayesian machines robustness against SEUs and SETs

2016 16th European Conference on Radiation and Its Effects on Components and Systems (RADECS), 2016, p.1-5

2016

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Fault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-cores Systems

2010 Ninth IEEE International Symposium on Network Computing and Applications, 2010, p.52-59

2010

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Multilanguage design of heterogeneous systems

International Conference on Hardware Software Codesign: Proceedings of the seventh international workshop on Hardware/software codesign, 1999, p.54-58

1999

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Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor

2011 Sixteenth IEEE European Test Symposium, 2011, p.93-98

2011

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Self-Recovering Parallel Applications in Multi-core Systems

2011 IEEE 10th International Symposium on Network Computing and Applications, 2011, p.51-58

2011

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Towards design and validation of mixed-technology SOCs

Great Lakes Symposium on VLSI: Proceedings of the 10th Great Lakes symposium on VLSI; 02-04 Mar. 2000, 2000, p.29-33

2000

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Scheduling and iming analysis of HW/SW on-chip communication in MP SoC design

2003 Design, Automation and Test in Europe Conference and Exhibition, 2003, p.132-137

2003

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Communication interface synthesis for multilanguage specifications

Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246), 1999, p.15-20

1999

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Automatic Code Generation for MPSoC Platform Starting From Simulink/Matlab : New Approach to Bridge the Gap between Algorithm and Architecture Design

2008 3rd International Conference on Information and Communication Technologies: From Theory to Applications, 2008, p.1-6

2008

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A generic architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip

Annales des télécommunications, 2004-07, Vol.59 (7-8), p.784-806

2004

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Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007, p.9-14

2007

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Assessing Contact Graph Routing Performance and Reliability in Distributed Satellite Constellations

Combining a performance estimation methodology with a hardware/software codesign flow supporting multiprocessor systems

Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation

Assessing the Static and Dynamic Sensitivity of a Commercial Off-the-Shelf Multicore Processor for Noncritical Avionic Applications

A fault-tolerant deadlock-free adaptive routing for on chip interconnects

Towards a tool for implementing delay-free ECC in embedded memories

Eliminating speed penalty in ECC protected memories

An efficient architecture model for systematic design of application-specific multiprocessor SoC

Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design

Design for test and reliability in ultimate CMOS

Multi-level communication synthesis of heterogeneous multilanguage specification

Design space exploration for hardware/software codesign of multiprocessor systems

Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes

Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs

Evidences of stochastic Bayesian machines robustness against SEUs and SETs

Fault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-cores Systems

Multilanguage design of heterogeneous systems

Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor

Self-Recovering Parallel Applications in Multi-core Systems

Towards design and validation of mixed-technology SOCs

Scheduling and iming analysis of HW/SW on-chip communication in MP SoC design

Communication interface synthesis for multilanguage specifications

Automatic Code Generation for MPSoC Platform Starting From Simulink/Matlab : New Approach to Bridge the Gap between Algorithm and Architecture Design

A generic architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip

Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design

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