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An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design

IEEE transactions on circuits and systems. II, Express briefs, 2008-12, Vol.55 (12), p.1234-1238

Chang, Yun-Nan

2008

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Architectures for digital filters using stochastic computing

2013 IEEE International Conference on Acoustics, Speech and Signal Processing, 2013, p.2697-2701

2013

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Predicting in-hospital mortality in adult non-traumatic emergency department patients: a retrospective comparison of the Modified Early Warning Score (MEWS) and machine learning approach

PeerJ (San Francisco, CA), 2021-08, Vol.9, p.e11988-e11988, Article e11988

2021

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Efficient Vector Graphics Rasterization Accelerator Using Optimized Scan-Line Buffer

IEEE transactions on very large scale integration (VLSI) systems, 2013-07, Vol.21 (7), p.1246-1259

2013

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A Multibank Memory-Based VLSI Architecture of DVB Symbol Deinterleaver

IEEE transactions on very large scale integration (VLSI) systems, 2010-05, Vol.18 (5), p.840-843

CHANG, Yun-Nan

2010

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A Fast Spline Curve Rendering Accelerator Architecture

IEEE transactions on circuits and systems. II, Express briefs, 2009-11, Vol.56 (11), p.870-874

Chang, Yun-Nan

2009

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Design of Low-cost IOU Circuit for Post-processing of Object Detection

2023 IEEE 12th Global Conference on Consumer Electronics (GCCE), 2023, p.407-408

Chang, Yun-Nan

2023

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An efficient pipelined FFT architecture

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2003-06, Vol.50 (6), p.322-325

2003

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A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder

IEEE journal of solid-state circuits, 2000-06, Vol.35 (6), p.826-834

2000

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An Efficient Curve-Scanline Intersection Locator Design for 2D Graphics Rendering

Journal of signal processing systems, 2015-04, Vol.79 (1), p.63-74

2015

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Digit-Serial Pipeline Sorter Architecture

Journal of signal processing systems, 2010-11, Vol.61 (2), p.241-249

Chang, Yun-Nan

2010

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An edge-list compression scheme for 2-D graphic system

2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 2010, p.513-516

2010

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An efficient hardware-software codesign of 3D rasterization module

2011 IEEE International Conference on Consumer Electronics -Berlin (ICCE-Berlin), 2011, p.15-16

Yun-Nan Chang

2011

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Design of VLSI sorting accelerator architecture

2008 51st Midwest Symposium on Circuits and Systems, 2008, p.878-881

2008

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A four-bank memory design of optimized semi-parallel polar decoder

2017 IEEE 9th International Conference on Communication Software and Networks (ICCSN), 2017, p.80-84

2017

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A low-cost dual-mode deinterleaver design

IEEE transactions on consumer electronics, 2008-05, Vol.54 (2), p.326-332

Chang, Y.-N.

2008

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An Efficient Design of H.264 Inter Interpolator with Bandwidth Optimization

Journal of signal processing systems, 2008-12, Vol.53 (3), p.435-448

2008

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Two-level hierarchical fill-buffer for graphics rendering systems

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS), 2013, p.1-4

Yun-Nan Chang

2013

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An integrated HDTV predictive pixel compensator for H.264/AVC decoder

2011 IEEE International Conference on IC Design & Technology, 2011, p.1-4

2011

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Design of a 2D graphics front-end rendering processor

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors, 2014, p.70-71

2014

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Design of an area-efficient partial-sum architecture for polar decoders based on new matrix generator

2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 2016, p.1-4

Yun-Nan Chang

2016

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Scaling Bit-Flexible Neural Networks

2019 International SoC Design Conference (ISOCC), 2019, p.253-254

2019

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Design of an efficient memory-based DVB-T channel decoder

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.5019-5022 Vol. 5

Yun-Nan Chang

2005

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Design of A Bit-Serial Artificial Neuron VLSI Architecture with Early Termination

2019 International Conference on Electronics, Information, and Communication (ICEIC), 2019, p.1-3

2019

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A Low-Cost Dual-Mode Deinterleaver Design

2007 Digest of Technical Papers International Conference on Consumer Electronics, 2007, p.1-2

2007

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An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design

Architectures for digital filters using stochastic computing

Predicting in-hospital mortality in adult non-traumatic emergency department patients: a retrospective comparison of the Modified Early Warning Score (MEWS) and machine learning approach

Efficient Vector Graphics Rasterization Accelerator Using Optimized Scan-Line Buffer

A Multibank Memory-Based VLSI Architecture of DVB Symbol Deinterleaver

A Fast Spline Curve Rendering Accelerator Architecture

Design of Low-cost IOU Circuit for Post-processing of Object Detection

An efficient pipelined FFT architecture

A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder

An Efficient Curve-Scanline Intersection Locator Design for 2D Graphics Rendering

Digit-Serial Pipeline Sorter Architecture

An edge-list compression scheme for 2-D graphic system

An efficient hardware-software codesign of 3D rasterization module

Design of VLSI sorting accelerator architecture

A four-bank memory design of optimized semi-parallel polar decoder

A low-cost dual-mode deinterleaver design

An Efficient Design of H.264 Inter Interpolator with Bandwidth Optimization

Two-level hierarchical fill-buffer for graphics rendering systems

An integrated HDTV predictive pixel compensator for H.264/AVC decoder

Design of a 2D graphics front-end rendering processor

Design of an area-efficient partial-sum architecture for polar decoders based on new matrix generator

Scaling Bit-Flexible Neural Networks

Design of an efficient memory-based DVB-T channel decoder

Design of A Bit-Serial Artificial Neuron VLSI Architecture with Early Termination

A Low-Cost Dual-Mode Deinterleaver Design

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