UB Paderborn / Katalog / Suche / in CDI

Free Razor: A Novel Voltage Scaling Low-Power Technique for Large SoC Designs

IEEE transactions on very large scale integration (VLSI) systems, 2015-11, Vol.23 (11), p.2431-2437

2015

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Novel 16QAM carrier recovery based on blind phase search

2014 The European Conference on Optical Communication (ECOC), 2014, p.1-3

2014

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Dense Hybrid Proposal Modulation for Lane Detection

IEEE transactions on circuits and systems for video technology, 2023-11, Vol.33 (11), p.1-1

2023

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Built-In Functional Tests for Silicon Validation and System Integration of Telecom SoC Designs

IEEE transactions on very large scale integration (VLSI) systems, 2011-04, Vol.19 (4), p.629-637

2011

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Fast detection of data retention faults and other SRAM cell open defects

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-01, Vol.25 (1), p.167-180

2006

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800G DSP ASIC Design Using Probabilistic Shaping and Digital Sub-Carrier Multiplexing

Journal of lightwave technology, 2020-09, Vol.38 (17), p.4744-4756

2020

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Testing ASICs with multiple identical cores

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-03, Vol.22 (3), p.327-336

2003

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Low power clocking strategies in deep submicron technologies

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, 2008, p.143-146

2008

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Dense 3-uniform hypergraphs containing a large clique

Science China. Mathematics, 2018-03, Vol.61 (3), p.577-592

2018

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Low Power SoC Memory BIST

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2006, p.197-205

2006

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Scan-based BIST fault diagnosis

IEEE transactions on computer-aided design of integrated circuits and systems, 1999-02, Vol.18 (2), p.203-211

1999

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Diagnosis of scan chain failures

Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223), 1998, p.217-222

Yuejian Wu

1998

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Designs for reducing test time of distributed small embedded SRAMs

19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings, 2004, p.120-128

2004

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Design and test of a 9-port SRAM for a 100 Gb/s STS-1 switch

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002), 2002, p.83-87

2002

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Single-reference multiple intermediate signature (SREMIS) analysis for BIST

IEEE transactions on computers, 1995-06, Vol.44 (6), p.817-825, Article 817

1995

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SRAM retention testing: zero incremental time integration with March algorithms

23rd IEEE VLSI Test Symposium (VTS'05), 2005, p.66-71

2005

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Interconnect delay fault testing with IEEE 1149.1

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), 1999, p.449-457

1999

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Shadow write and read for at-speed BIST of TDM SRAMs

Proceedings International Test Conference 2001 (Cat. No.01CH37260), 2001, p.985-994

2001

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BIST fault diagnosis in scan-based VLSI environments

Proceedings International Test Conference 1996. Test and Design Validity, 1996, p.48-57

1996

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Built-in self-test for multi-port RAMs

Proceedings Sixth Asian Test Symposium (ATS'97), 1997, p.398-403

1997

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Promising DSP Techniques to Increase Long Haul Transmission Capacity

2023 Optical Fiber Communications Conference and Exhibition (OFC), 2023, p.1-3

2023

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854 Gb/s superchannel InP transmitter and receiver photonic integrated circuits utilizing real-time detection of PM-8QAM

OFC/NFOEC, 2012, p.1-3

2012

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Built-in functional tests for fast validation of a 40Gbps coherent optical receiver SoC ASIC

2008 IEEE International SOC Conference, 2008, p.55-58

2008

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Accelerated path delay fault simulation

Digest of Papers. 1992 IEEE VLSI Test Symposium, 1992, p.1-6

1992

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Low power decoding of BCH codes

2004 IEEE International Symposium on Circuits and Systems (ISCAS), 2004, Vol.2, p.II-369

Yuejian Wu

2004

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Free Razor: A Novel Voltage Scaling Low-Power Technique for Large SoC Designs

Novel 16QAM carrier recovery based on blind phase search

Dense Hybrid Proposal Modulation for Lane Detection

Built-In Functional Tests for Silicon Validation and System Integration of Telecom SoC Designs

Fast detection of data retention faults and other SRAM cell open defects

800G DSP ASIC Design Using Probabilistic Shaping and Digital Sub-Carrier Multiplexing

Testing ASICs with multiple identical cores

Low power clocking strategies in deep submicron technologies

Dense 3-uniform hypergraphs containing a large clique

Low Power SoC Memory BIST

Scan-based BIST fault diagnosis

Diagnosis of scan chain failures

Designs for reducing test time of distributed small embedded SRAMs

Design and test of a 9-port SRAM for a 100 Gb/s STS-1 switch

Single-reference multiple intermediate signature (SREMIS) analysis for BIST

SRAM retention testing: zero incremental time integration with March algorithms

Interconnect delay fault testing with IEEE 1149.1

Shadow write and read for at-speed BIST of TDM SRAMs

BIST fault diagnosis in scan-based VLSI environments

Built-in self-test for multi-port RAMs

Promising DSP Techniques to Increase Long Haul Transmission Capacity

854 Gb/s superchannel InP transmitter and receiver photonic integrated circuits utilizing real-time detection of PM-8QAM

Built-in functional tests for fast validation of a 40Gbps coherent optical receiver SoC ASIC

Accelerated path delay fault simulation

Low power decoding of BCH codes

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