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High Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture

Yue, Jinshan

2024

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Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-10, Vol.36 (10), p.1660-1673

2017

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A Survey of Computing-in-Memory Processor: From Circuit to Application

IEEE open journal of solid-state circuits, 2024, Vol.4, p.25-42

2024

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Trending IC design directions in 2022

Journal of semiconductors, 2022-07, Vol.43 (7), p.71401-55

2022

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Fully Binarized Graph Convolutional Network Accelerator Based on In‐Memory Computing with Resistive Random‐Access Memory

Advanced intelligent systems, 2024-07, Vol.6 (7), p.n/a

2024

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Hardware Implementation of Next Generation Reservoir Computing with RRAM‐Based Hybrid Digital‐Analog System

Advanced intelligent systems, 2024-10, Vol.6 (10), p.n/a

2024

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CORAL: Coarse-grained reconfigurable architecture for Convolutional Neural Networks

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2017, p.1-6

2017

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STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS

IEEE journal of solid-state circuits, 2020-02, Vol.55 (2), p.465-477

2020

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Accuracy Optimization With the Framework of Non-Volatile Computing-In-Memory Systems

IEEE transactions on circuits and systems. I, Regular papers, 2022-02, Vol.69 (2), p.518-529

2022

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A 28-nm Energy-Efficient Sparse Neural Network Processor for Point Cloud Applications Using Block-Wise Online Neighbor Searching

IEEE journal of solid-state circuits, 2024-09, Vol.59 (9), p.3070-3081

2024

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Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6

2016

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A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity

IEEE journal of solid-state circuits, 2024-06, p.1-15

2024

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Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers

2018 IEEE Symposium on VLSI Circuits, 2018, p.33-34

2018

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Recent progress in InGaZnO FETs for high-density 2T0C DRAM applications

Science China. Information sciences, 2023-10, Vol.66 (10), p.200404, Article 200404

2023

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P 3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer

IEEE transactions on circuits and systems. I, Regular papers, 2023-12, Vol.70 (12), p.4938-4948

2023

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LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design

IEEE transactions on circuits and systems. II, Express briefs, 2024-02, Vol.71 (2), p.852-856

2024

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A Multi-Chiplet Computing-in-Memory Architecture Exploration Framework Based on Various CIM Devices

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-06, p.1-1

2024

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An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree

IEEE transactions on circuits and systems. II, Express briefs, 2023-02, Vol.70 (2), p.416-420

2023

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A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference

IEEE journal of solid-state circuits, 2024-08, p.1-12

2024

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A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture

IEEE journal of solid-state circuits, 2024-08, Vol.59 (8), p.2630-2643

2024

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A 40-nm SONOS Digital CIM Using Simplified LUT Multiplier and Continuous Sample-Hold Sense Amplifier for AI Edge Inference

IEEE transactions on very large scale integration (VLSI) systems, 2023-12, Vol.31 (12), p.2044-2052

2023

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P3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer

IEEE transactions on circuits and systems. I, Regular papers, 2023-12, Vol.70 (12), p.4938-4948

2023

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STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse

IEEE journal of solid-state circuits, 2022-08, Vol.57 (8), p.2560-2573

2022

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Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems

IEEE transactions on circuits and systems. II, Express briefs, 2022-07, Vol.69 (7), p.3144-3148

2022

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SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity-Compensated Fully Parallel Analog Adder Tree

IEEE transactions on circuits and systems. I, Regular papers, 2023-07, Vol.70 (7), p.1-12

2023

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High Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture

Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes

A Survey of Computing-in-Memory Processor: From Circuit to Application

Trending IC design directions in 2022

Fully Binarized Graph Convolutional Network Accelerator Based on In‐Memory Computing with Resistive Random‐Access Memory

Hardware Implementation of Next Generation Reservoir Computing with RRAM‐Based Hybrid Digital‐Analog System

CORAL: Coarse-grained reconfigurable architecture for Convolutional Neural Networks

STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS

Accuracy Optimization With the Framework of Non-Volatile Computing-In-Memory Systems

A 28-nm Energy-Efficient Sparse Neural Network Processor for Point Cloud Applications Using Block-Wise Online Neighbor Searching

Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead

A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity

Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers

Recent progress in InGaZnO FETs for high-density 2T0C DRAM applications

P 3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer

LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design

A Multi-Chiplet Computing-in-Memory Architecture Exploration Framework Based on Various CIM Devices

An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree

A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference

A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture

A 40-nm SONOS Digital CIM Using Simplified LUT Multiplier and Continuous Sample-Hold Sense Amplifier for AI Edge Inference

P3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer

STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse

Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems

SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity-Compensated Fully Parallel Analog Adder Tree

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