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μBrain: An Event-Driven and Fully Synthesizable Architecture for Spiking Neural Networks

Frontiers in neuroscience, 2021-05, Vol.15, p.664208-664208

2021

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On Practical Issues for Stochastic STDP Hardware With 1-bit Synaptic Weights

Frontiers in neuroscience, 2018-10, Vol.12, p.665-665

2018

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SENECA: building a fully digital neuromorphic processor, design trade-offs and challenges

Frontiers in neuroscience, 2023-06, Vol.17, p.1187252-1187252

2023

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Unsupervised learning of repeating patterns using a novel STDP based algorithm

Journal of vision (Charlottesville, Va.), 2017-08, Vol.17 (10), p.1079

2017

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Optimizing event-based neural networks on digital neuromorphic architecture: a comprehensive design space exploration

Frontiers in neuroscience, 2024-03, Vol.18, p.1335422-1335422

2024

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Tutorial on memristor-based computing for smart edge applications

Memories - Materials, Devices, Circuits and Systems, 2023-07, Vol.4, p.100025, Article 100025

2023

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NeuronFlow: a neuromorphic processor architecture for Live AI applications

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, p.840-845

2020

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Multidie 3-D Stacking of Memory Dominated Neuromorphic Architectures

IEEE transactions on very large scale integration (VLSI) systems, 2024-07, p.1-0

2024

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Active Perception With Dynamic Vision Sensors. Minimum Saccades With Optimum Recognition

IEEE transactions on biomedical circuits and systems, 2018-08, Vol.12 (4), p.927-939

2018

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Empirical study on the efficiency of Spiking Neural Networks with axonal delays, and algorithm-hardware benchmarking

2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5

2023

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Energy-efficient In-Memory Address Calculation

ACM transactions on architecture and code optimization, 2022-12, Vol.19 (4), p.1-16

2022

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Aircraft Marshaling Signals Dataset of FMCW Radar and Event-Based Camera for Sensor Fusion

2023 IEEE Radar Conference (RadarConf23), 2023, p.01-06

2023

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Co-optimized training of models with synaptic delays for digital neuromorphic accelerators

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems

IEEE transactions on biomedical circuits and systems, 2017-10, Vol.11 (5), p.1133-1147

2017

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Asynchronous Spiking Neurons, the Natural Key to Exploit Temporal Sparsity

IEEE journal on emerging and selected topics in circuits and systems, 2019-12, Vol.9 (4), p.668-678

2019

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Open the box of digital neuromorphic processor: Towards effective algorithm-hardware co-design

2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5

2023

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Hybrid Neural Network, An Efficient Low-Power Digital Hardware Implementation of Event-based Artificial Neural Network

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, p.1-5

2018

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Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links

IEEE transactions on circuits and systems. II, Express briefs, 2016-08, Vol.63 (8), p.763-767

2016

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Delta Activation Layer exploits temporal sparsity for efficient embedded video processing

2022 International Joint Conference on Neural Networks (IJCNN), 2022, p.01-10

2022

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NeuronFlow: a neuromorphic processor architecture for live AI applications

Proceedings of the 23rd Conference on Design, Automation and Test in Europe, 2020, p.840-845

2020

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Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, p.1-4

2018

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SpArNet: Sparse Asynchronous Neural Network execution for energy efficient inference

2020 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2020, p.256-260

2020

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SENSIM: An Event-driven Parallel Simulator for Multi-core Neuromorphic Systems

2024 International Joint Conference on Neural Networks (IJCNN), 2024, p.1-6

2024

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SENeCA: Scalable Energy-efficient Neuromorphic Computer Architecture

2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022, p.371-374

2022

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Conversion of Synchronous Artificial Neural Network to Asynchronous Spiking Neural Network using sigma-delta quantization

2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2019, p.81-85

2019

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μBrain: An Event-Driven and Fully Synthesizable Architecture for Spiking Neural Networks

On Practical Issues for Stochastic STDP Hardware With 1-bit Synaptic Weights

SENECA: building a fully digital neuromorphic processor, design trade-offs and challenges

Unsupervised learning of repeating patterns using a novel STDP based algorithm

Optimizing event-based neural networks on digital neuromorphic architecture: a comprehensive design space exploration

Tutorial on memristor-based computing for smart edge applications

NeuronFlow: a neuromorphic processor architecture for Live AI applications

Multidie 3-D Stacking of Memory Dominated Neuromorphic Architectures

Active Perception With Dynamic Vision Sensors. Minimum Saccades With Optimum Recognition

Empirical study on the efficiency of Spiking Neural Networks with axonal delays, and algorithm-hardware benchmarking

Energy-efficient In-Memory Address Calculation

Aircraft Marshaling Signals Dataset of FMCW Radar and Event-Based Camera for Sensor Fusion

Co-optimized training of models with synaptic delays for digital neuromorphic accelerators

On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems

Asynchronous Spiking Neurons, the Natural Key to Exploit Temporal Sparsity

Open the box of digital neuromorphic processor: Towards effective algorithm-hardware co-design

Hybrid Neural Network, An Efficient Low-Power Digital Hardware Implementation of Event-based Artificial Neural Network

Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links

Delta Activation Layer exploits temporal sparsity for efficient embedded video processing

NeuronFlow: a neuromorphic processor architecture for live AI applications

Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker

SpArNet: Sparse Asynchronous Neural Network execution for energy efficient inference

SENSIM: An Event-driven Parallel Simulator for Multi-core Neuromorphic Systems

SENeCA: Scalable Energy-efficient Neuromorphic Computer Architecture

Conversion of Synchronous Artificial Neural Network to Asynchronous Spiking Neural Network using sigma-delta quantization

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