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Variation-Tolerant Sensing Circuit for Ultralow-Voltage Operation of Spin-Torque Transfer Magnetic RAM

IEEE transactions on circuits and systems. II, Express briefs, 2017-05, Vol.64 (5), p.570-574

2017

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Fast and efficient STT switching in MTJ using additional transient pulse current

Applied physics letters, 2017-06, Vol.110 (23)

2017

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Revisiting virtual L1 caches: A practical design using dynamic synonym remapping

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2016, p.212-224

2016

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Two Billion Devices and Counting

IEEE MICRO, 2018-01, Vol.38 (1), p.6-21

2018

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New efficient FFT algorithm and pipeline implementation results for OFDM/DMT applications

IEEE transactions on consumer electronics, 2003-02, Vol.49 (1), p.14-20

2003

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A Bandgap Reference Circuit with Feedback Loop for Decrement of Effects from PVT Variations

Journal of the Institute of Electronics and Information Engineers, 2023-02, Vol.60 (2), p.105-112

2023

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Electro-Optical Characteristics of Liquid Crystal Device With Nanoscale Molybdenum Trioxide (\hbox) Thin Films

IEEE electron device letters, 2012-10, Vol.33 (10), p.1423-1425

2012

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A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

Electronics (Basel), 2020-11, Vol.9 (11), p.1769

2020

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High Speed Back-Bias Voltage (VBB) Generator with Improved Pumping Current

Electronics (Basel), 2020-11, Vol.9 (11), p.1835

2020

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A High Speed Modified Dickson Charge Pump

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, p.1-5

2021

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Electrooptical Properties of Single-Walled Carbon-Nanotube Mixed Liquid-Crystal Cells With Rubbed and Ion-Beam-Treated Alignment Layers

Journal of display technology, 2011-12, Vol.7 (12), p.644-648

2011

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STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-05, Vol.41 (5), p.1330-1343

2022

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Convergence analysis of the cascade second-order adaptive line equalizer

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2006-06, Vol.53 (6), p.507-511

2006

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A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor

IEEE journal of solid-state circuits, 2003-04, Vol.38 (4), p.631-640

2003

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Reducing address translation overheads with virtual caching

Yoon, Hongil

2017

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Efficient Implementation of Single Error Correction and Double Error Detection Code with Check Bit Pre-computation for Memories

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2012, 12(4), 48, pp.418-425

2012

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Implementation of wireless LAN baseband processor based on space-frequency OFDM transmit diversity scheme

IEEE transactions on consumer electronics, 2005-05, Vol.51 (2), p.393-398

2005

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Efficient Implementation of Single Error Correction and Double Error Detection Code with Check Bit Pre-computation for Memories

Journal of semiconductor technology and science, 2012, Vol.12 (4), p.418-425

2012

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Efficient Implementation of Single Error Correction and Double Error Detection Code with Check Bit Precomputation for Memories

Journal of semiconductor technology and science, 2012, Vol.12 (4), p.418-425

2012

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Variation-tolerant and low power look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile field programmable gate array (FPGA)

2016 International SoC Design Conference (ISOCC), 2016, p.101-102

2016

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Self-correcting check bit generator of error correction codes for memories

IEICE Electronics Express, 2013-01, Vol.10 (6), p.20130103-20130103

2013

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Highly robust and sensitive charge transfer sense amplifier for ultra-low voltage DRAMs

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013), 2013, p.227-232

2013

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Design and Implementation of MIMO-OFDM Baseband Processor for High-Speed Wireless LANs

IEEE transactions on circuits and systems. II, Express briefs, 2007-07, Vol.54 (7), p.631-635

2007

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A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

IEEE journal of solid-state circuits, 1999-11, Vol.34 (11), p.1589-1599

1999

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Filtering Translation Bandwidth with Virtual Caching

Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018, p.113-127

2018

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Variation-Tolerant Sensing Circuit for Ultralow-Voltage Operation of Spin-Torque Transfer Magnetic RAM

Fast and efficient STT switching in MTJ using additional transient pulse current

Revisiting virtual L1 caches: A practical design using dynamic synonym remapping

Two Billion Devices and Counting

New efficient FFT algorithm and pipeline implementation results for OFDM/DMT applications

A Bandgap Reference Circuit with Feedback Loop for Decrement of Effects from PVT Variations

Electro-Optical Characteristics of Liquid Crystal Device With Nanoscale Molybdenum Trioxide (\hbox) Thin Films

A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

High Speed Back-Bias Voltage (VBB) Generator with Improved Pumping Current

A High Speed Modified Dickson Charge Pump

Electrooptical Properties of Single-Walled Carbon-Nanotube Mixed Liquid-Crystal Cells With Rubbed and Ion-Beam-Treated Alignment Layers

STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment

Convergence analysis of the cascade second-order adaptive line equalizer

A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor

Reducing address translation overheads with virtual caching

Efficient Implementation of Single Error Correction and Double Error Detection Code with Check Bit Pre-computation for Memories

Implementation of wireless LAN baseband processor based on space-frequency OFDM transmit diversity scheme

Efficient Implementation of Single Error Correction and Double Error Detection Code with Check Bit Pre-computation for Memories

Efficient Implementation of Single Error Correction and Double Error Detection Code with Check Bit Precomputation for Memories

Variation-tolerant and low power look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile field programmable gate array (FPGA)

Self-correcting check bit generator of error correction codes for memories

Highly robust and sensitive charge transfer sense amplifier for ultra-low voltage DRAMs

Design and Implementation of MIMO-OFDM Baseband Processor for High-Speed Wireless LANs

A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

Filtering Translation Bandwidth with Virtual Caching

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