UB Paderborn / Katalog / Suche / in CDI

Hybrid Precision Floating-Point (HPFP) Selection to Optimize Hardware-Constrained Accelerator for CNN Training

Sensors (Basel, Switzerland), 2024-04, Vol.24 (7), p.2145

2024

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Efficient Pruning for Successive-Cancellation Decoding of Polar Codes

IEEE communications letters, 2016-12, Vol.20 (12), p.2362-2365

2016

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Efficient Partially-parallel NTT Processor for Lattice-based Post-quantum Cryptography

Journal of semiconductor technology and science, 2022-12, Vol.22 (6), p.459-474

2022

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TRNG-PUF Integration Utilizing Programmable Delay Logics on FPGAs

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2024, 24(3), 117, pp.240-248

2024

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Efficient Parallel Architecture for Linear Feedback Shift Registers

IEEE transactions on circuits and systems. II, Express briefs, 2015-11, Vol.62 (11), p.1068-1072

2015

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High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives

IEEE transactions on very large scale integration (VLSI) systems, 2014-05, Vol.22 (5), p.1183-1187

2014

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Energy-efficient Key-equation Solving Algorithm for BCH Decoding

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2018, 18(4), 82, pp.518-524

2018

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Low-Power Parallel Chien Search Architecture Using a Two-Step Approach

IEEE transactions on circuits and systems. II, Express briefs, 2016-03, Vol.63 (3), p.269-273

2016

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6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers

2012 IEEE International Solid-State Circuits Conference, 2012, p.426-428

2012

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Assessing the main and spillover effects of Seattle's minimum wage on establishment decisions

Regional science and urban economics, 2023-03, Vol.99, p.103865, Article 103865

2023

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Area-Efficient Multimode Encoding Architecture for Long BCH Codes

IEEE transactions on circuits and systems. II, Express briefs, 2013-12, Vol.60 (12), p.872-876

2013

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Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization

IEEE transactions on circuits and systems. II, Express briefs, 2011-08, Vol.58 (8), p.522-526

2011

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Area-optimized Syndrome Calculation for ReedSolomon Decoder

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2018, 18(5), 83, pp.609-615

2018

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Approaches to Extend FPGA Reverse-Engineering Technology from ISE to Vivado

Electronics (Basel), 2024-03, Vol.13 (6), p.1100

2024

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The Effects of the Opioid Crisis on Employment: Evidence from Labor Market Flows

The Journal of human resources, 2023-04, p.1121

2023

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Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism

IEEE transactions on very large scale integration (VLSI) systems, 2021-06, Vol.29 (6), p.1083-1094

2021

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Area-Efficient Differential Fault Tolerance Encoding for Finite State Machines

Electronics (Basel), 2020-07, Vol.9 (7), p.1110

2020

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Fast Logic Function Extraction of LUT from Bitstream in Xilinx FPGA

Electronics (Basel), 2020, Vol.9 (7), p.1132

2020

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Essays on Labor and Urban Economics

Yoo, Hoyoung

2024

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Efficient Processing-in-Memory System Based on RISC-V Instruction Set Architecture

Electronics (Basel), 2024-08, Vol.13 (15), p.2971

2024

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Area-Efficient Early-Termination Technique for Belief-Propagation Polar Decoders

Electronics (Basel), 2019-09, Vol.8 (9), p.1001

2019

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S-Box Attack Using FPGA Reverse Engineering for Lightweight Cryptography

IEEE internet of things journal, 2022-12, Vol.9 (24), p.25165-25180

2022

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Small-area parallel syndrome calculation for strong BCH decoding

2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2012, p.1609-1612

2012

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Partially Parallel Encoder Architecture for Long Polar Codes

IEEE transactions on circuits and systems. II, Express briefs, 2015-03, Vol.62 (3), p.306-310

2015

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Resource usage of LTE networks for machine-to-Machine group communications: Modeling and analysis

Computers & electrical engineering, 2018-10, Vol.71, p.321-330

2018

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Hybrid Precision Floating-Point (HPFP) Selection to Optimize Hardware-Constrained Accelerator for CNN Training

Efficient Pruning for Successive-Cancellation Decoding of Polar Codes

Efficient Partially-parallel NTT Processor for Lattice-based Post-quantum Cryptography

TRNG-PUF Integration Utilizing Programmable Delay Logics on FPGAs

Efficient Parallel Architecture for Linear Feedback Shift Registers

High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives

Energy-efficient Key-equation Solving Algorithm for BCH Decoding

Low-Power Parallel Chien Search Architecture Using a Two-Step Approach

6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers

Assessing the main and spillover effects of Seattle's minimum wage on establishment decisions

Area-Efficient Multimode Encoding Architecture for Long BCH Codes

Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization

Area-optimized Syndrome Calculation for ReedSolomon Decoder

Approaches to Extend FPGA Reverse-Engineering Technology from ISE to Vivado

The Effects of the Opioid Crisis on Employment: Evidence from Labor Market Flows

Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism

Area-Efficient Differential Fault Tolerance Encoding for Finite State Machines

Fast Logic Function Extraction of LUT from Bitstream in Xilinx FPGA

Essays on Labor and Urban Economics

Efficient Processing-in-Memory System Based on RISC-V Instruction Set Architecture

Area-Efficient Early-Termination Technique for Belief-Propagation Polar Decoders

S-Box Attack Using FPGA Reverse Engineering for Lightweight Cryptography

Small-area parallel syndrome calculation for strong BCH decoding

Partially Parallel Encoder Architecture for Long Polar Codes

Resource usage of LTE networks for machine-to-Machine group communications: Modeling and analysis

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