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Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns

IEEE transactions on very large scale integration (VLSI) systems, 2017-08, Vol.25 (8), p.2220-2233

2017

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A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications

IEEE journal of solid-state circuits, 2018-04, Vol.53 (4), p.968-982

2018

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A Fast and Power-Efficient Hardware Architecture for Non-Maximum Suppression

IEEE transactions on circuits and systems. II, Express briefs, 2019-11, Vol.66 (11), p.1870-1874

2019

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Copper-substituted NaxMO2 (M = Fe, Mn) cathodes for sodium ion batteries: Enhanced cycling stability through suppression of Mn(III) formation

Chemical engineering journal (Lausanne, Switzerland : 1996), 2021-02, Vol.406, p.126830, Article 126830

2021

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Low-Computing-Load, High-Parallelism Detection Method Based on Chebyshev Iteration for Massive MIMO Systems With VLSI Architecture

IEEE transactions on signal processing, 2017-07, Vol.65 (14), p.3775-3788

2017

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An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation

IEEE transactions on circuits and systems. I, Regular papers, 2022-07, Vol.69 (7), p.2655-2668

2022

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Fast traffic sign recognition with a rotation invariant binary pattern based feature

Sensors (Basel, Switzerland), 2015-01, Vol.15 (1), p.2161-2180

2015

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An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-08, Vol.34 (8), p.1264-1277

2015

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Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-12, Vol.37 (12), p.3081-3094

2018

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A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems

IEEE transactions on parallel and distributed systems, 2017-03, Vol.28 (3), p.662-676

2017

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Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures

IEEE transactions on very large scale integration (VLSI) systems, 2016-05, Vol.24 (5), p.1895-1908

2016

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Characterization of microbial-induced concrete corrosion by combining morphology observation and fluorescence staining

Case Studies in Construction Materials, 2022-12, Vol.17, p.e01586, Article e01586

2022

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A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator

IEEE transactions on circuits and systems for video technology, 2016-08, Vol.26 (8), p.1532-1543

2016

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A 1/2.5 inch VGA 400 fps CMOS Image Sensor With High Sensitivity for Machine Vision

IEEE journal of solid-state circuits, 2014-10, Vol.49 (10), p.2342-2351

2014

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Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory

IEEE transactions on parallel and distributed systems, 2017-09, Vol.28 (9), p.2471-2485

2017

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An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

IEEE transactions on multimedia, 2015-10, Vol.17 (10), p.1706-1720

2015

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Trigger-Centric Loop Mapping on CGRAs

IEEE transactions on very large scale integration (VLSI) systems, 2016-05, Vol.24 (5), p.1998-2002

2016

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A 1.58 Gbps/W 0.40 Gbps/mm2 ASIC Implementation of MMSE Detection for 128\times 8~64 -QAM Massive MIMO in 65 nm CMOS

IEEE transactions on circuits and systems. I, Regular papers, 2018-05, Vol.65 (5), p.1717-1730

2018

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Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks

IEEE transactions on information forensics and security, 2017-02, Vol.12 (2), p.309-322

2017

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A real-time time-consistent 2D-to-3D video conversion system using color histogram

IEEE transactions on consumer electronics, 2015-11, Vol.61 (4), p.524-530

2015

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CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays

IEEE transactions on parallel and distributed systems, 2017-01, Vol.28 (1), p.29-43

2017

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Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture

IEEE transactions on information forensics and security, 2016-06, Vol.11 (6), p.1151-1164

2016

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A Fast Integral Image Computing Hardware Architecture With High Power and Area Efficiency

IEEE transactions on circuits and systems. II, Express briefs, 2015-01, Vol.62 (1), p.75-79

2015

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Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures

IEEE transactions on very large scale integration (VLSI) systems, 2015-11, Vol.23 (11), p.2581-2594

2015

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On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time

IEEE transactions on very large scale integration (VLSI) systems, 2014-05, Vol.22 (5), p.983-994

2014

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Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns

A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications

A Fast and Power-Efficient Hardware Architecture for Non-Maximum Suppression

Copper-substituted NaxMO2 (M = Fe, Mn) cathodes for sodium ion batteries: Enhanced cycling stability through suppression of Mn(III) formation

Low-Computing-Load, High-Parallelism Detection Method Based on Chebyshev Iteration for Massive MIMO Systems With VLSI Architecture

An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation

Fast traffic sign recognition with a rotation invariant binary pattern based feature

An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures

Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms

A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems

Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures

Characterization of microbial-induced concrete corrosion by combining morphology observation and fluorescence staining

A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator

A 1/2.5 inch VGA 400 fps CMOS Image Sensor With High Sensitivity for Machine Vision

Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

Trigger-Centric Loop Mapping on CGRAs

A 1.58 Gbps/W 0.40 Gbps/mm2 ASIC Implementation of MMSE Detection for 128\times 8~64 -QAM Massive MIMO in 65 nm CMOS

Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks

A real-time time-consistent 2D-to-3D video conversion system using color histogram

CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays

Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture

A Fast Integral Image Computing Hardware Architecture With High Power and Area Efficiency

Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures

On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time

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