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A 0.0056-mm 2 −249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs

IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.88-98

2019

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A 0.0056-mm2 −249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs

IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.88-98

2019

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A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and −249dB FOM

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.118-120

2018

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A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS

2012 Proceedings of the ESSCIRC (ESSCIRC), 2012, p.377-380

2012

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0.026µm2 high performance Embedded DRAM in 22nm technology for server and SOC applications

2014 IEEE International Electron Devices Meeting, 2014, p.19.4.1-19.4.4

2014

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A 0.032-mm 2 0.15-V Three-Stage Charge-Pump Scheme Using a Differential Bootstrapped Ring-VCO for Energy-Harvesting Applications

IEEE transactions on circuits and systems. II, Express briefs, 2018-02, Vol.65 (2), p.146-150

2018

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A 0.032-mm2 0.15-V Three-Stage Charge-Pump Scheme Using a Differential Bootstrapped Ring-VCO for Energy-Harvesting Applications

IEEE transactions on circuits and systems. II, Express briefs, 2018-02, Vol.65 (2), p.146-150

2018

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A 0.039um2 high performance eDRAM cell based on 32nm High-K/Metal SOI technology

2010 International Electron Devices Meeting, 2010, p.27.5.1-27.5.4

2010

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A 0.12-mm 2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-$\mu$ s Settling Time for Multi-ISM-Band ULP Radios

IEEE transactions on circuits and systems. I, Regular papers, 2019-09, Vol.66 (9), p.3307-3316

2019

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A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8- \mu s Settling Time for Multi-ISM-Band ULP Radios

IEEE transactions on circuits and systems. I, Regular papers, 2019-09, Vol.66 (9), p.3307-3316

2019

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A 0.15-V, 44.73% PCE charge pump with CMOS differential ring-VCO for energy harvesting systems

Analog integrated circuits and signal processing, 2022, Vol.111 (1), p.35-43

2022

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0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking

IEEE journal of solid-state circuits, 2012-08, Vol.47 (8), p.1842-1853

2012

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0.18 /spl mu/m SiGe BiCMOS technology for wireless and 40 Gb/s communication products

Proceedings of the 2001 BIPOLAR/BiCMOS Circuits and Technology Meeting (Cat. No.01CH37212), 2001, p.147-150

2001

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A 0.18-V 382-[Formula Omitted]W Bluetooth Low-Energy Receiver Front-End With 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS

IEEE journal of solid-state circuits, 2018-01, Vol.53 (6), p.1618

2018

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A 0.18-V 382- \mu W Bluetooth Low-Energy Receiver Front-End With 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS

IEEE journal of solid-state circuits, 2018-06, Vol.53 (6), p.1618-1627

2018

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A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS

IEEE journal of solid-state circuits, 2019-05, Vol.54 (5), p.1351-1362

2019

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A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.450-452

2018

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A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration

IEEE journal of solid-state circuits, 2011-12, Vol.46 (12), p.2759-2771

2011

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A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration

2011 IEEE International Solid-State Circuits Conference, 2011, p.92-94

2011

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A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance

IEEE journal of solid-state circuits, 2011-12, Vol.46 (12), p.3150-3162

2011

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A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance

2011 IEEE International Solid-State Circuits Conference, 2011, p.438-450

2011

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A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM

IEEE transactions on circuits and systems. II, Express briefs, 2019-02, Vol.66 (2), p.157-161

2019

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A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking

IEEE journal of solid-state circuits, 2011-08, Vol.46 (8), p.1870-1880

2011

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A 0.9-V Input Discontinuous-Conduction-Mode Boost Converter With CMOS-Control Rectifier

IEEE journal of solid-state circuits, 2008-09, Vol.43 (9), p.2036-2046

2008

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014 IL-27 induces IL-15 production to facilitate T cell survival in allergic contact dermatitis

Journal of investigative dermatology, 2020-07, Vol.140 (7), p.S2-S2

2020

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A 0.0056-mm 2 −249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs

A 0.0056-mm2 −249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs

A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and −249dB FOM

A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS

0.026µm2 high performance Embedded DRAM in 22nm technology for server and SOC applications

A 0.032-mm 2 0.15-V Three-Stage Charge-Pump Scheme Using a Differential Bootstrapped Ring-VCO for Energy-Harvesting Applications

A 0.032-mm2 0.15-V Three-Stage Charge-Pump Scheme Using a Differential Bootstrapped Ring-VCO for Energy-Harvesting Applications

A 0.039um2 high performance eDRAM cell based on 32nm High-K/Metal SOI technology

A 0.12-mm 2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-$\mu$ s Settling Time for Multi-ISM-Band ULP Radios

A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8- \mu s Settling Time for Multi-ISM-Band ULP Radios

A 0.15-V, 44.73% PCE charge pump with CMOS differential ring-VCO for energy harvesting systems

0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking

0.18 /spl mu/m SiGe BiCMOS technology for wireless and 40 Gb/s communication products

A 0.18-V 382-[Formula Omitted]W Bluetooth Low-Energy Receiver Front-End With 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS

A 0.18-V 382- \mu W Bluetooth Low-Energy Receiver Front-End With 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS

A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS

A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS

A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration

A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration

A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance

A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance

A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM

A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking

A 0.9-V Input Discontinuous-Conduction-Mode Boost Converter With CMOS-Control Rectifier

014 IL-27 induces IL-15 production to facilitate T cell survival in allergic contact dermatitis

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