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Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Journal of electronic materials, 2011-07, Vol.40 (7), p.1584-1612, Article 1584

2011

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Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance

IEEE transactions on electron devices, 2015-05, Vol.62 (5), p.1411-1418

2015

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IEEE_Xplore

Ultrathin strained-SOI by stress balance on compliant substrates and FET performance

IEEE transactions on electron devices, 2005-10, Vol.52 (10), p.2207-2214

2005

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IEEE_Xplore

Buckling suppression of SiGe islands on compliant substrates

Journal of applied physics, 2003-11, Vol.94 (10), p.6875-6882

2003

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Nanopatterning of Si/SiGe electrical devices by atomic force microscopy oxidation

Applied physics letters, 2002-10, Vol.81 (17), p.3263-3265

2002

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Study of sigma-shaped source/drain recesses for embedded-SiGe pMOSFETs

Microelectronic engineering, 2017-09, Vol.181, p.22-28

2017

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FinFETs using reverse substrate layer with improved gate capacitance characteristics for subthreshold application

Solid-state electronics, 2015-02, Vol.104, p.116-121

2015

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Will SOI have a life for the low-power market?

2008 IEEE International SOI Conference, 2008, p.15-16

2008

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IEEE_Xplore

Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22 nm all-last high-k/metal-gate pMOSFETs

Solid-state electronics, 2016-09, Vol.123, p.38-43

2016

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Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22nm all-last high-k/metal-gate pMOSFETs

Solid-state electronics, 2016-09, Vol.123, p.38-43

2016

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Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 22 nm node pMOSFETs

Solid-state electronics, 2015-12, Vol.114, p.43

2015

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Rapid yield ramp using closed loop DFM and overlay process window qualification flow

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2018, p.231-233

2018

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IEEE_Xplore

Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 22nm node pMOSFETs

Solid-state electronics, 2015-12, Vol.114, p.43-48

2015

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Punch through stop layer optimization in bulk FinFETs

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014, p.1-3

2014

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Study of electron mobility on silicon with different crystalline orientations

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, 2012, p.1-3

2012

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IEEE_Xplore

Tunable uniaxial vs biaxial in-plane strain using compliant substrates

Applied physics letters, 2005-08, Vol.87 (6), p.061922-061922-3

2005

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Performance optimization of n-MOSFETs using asymmetric interfacial oxide layer

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010, p.1901-1903

2010

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IEEE_Xplore

Low leakage bulk silicon substrate based SDOI FINFETs

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010, p.1820-1822

2010

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IEEE_Xplore

High-germanium-content SiGe islands formed on compliant oxide by SiGe oxidation

Applied physics letters, 2004-05, Vol.84 (18), p.3624-3626

2004

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Advancement of maxillary anterior segment by distraction osteogenesis for severe maxillary retrusion in cleft lip and palate

Chinese medical journal, 2014, Vol.127 (3), p.500-505

2014

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Strain relaxation of silicon-germanium on compliant borophosphosilicate glass and its applications

Yin, Haizhou

2004

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ProQuest

35nm SOI-CMOS for Sub-Ambient Temperature Operation

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2007, p.1-2

2007

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IEEE_Xplore

Catalytic methanation of syngas over Ni-based catalysts with different supports

Chinese journal of chemical engineering, 2017-05, Vol.25 (5), p.602-608

2017

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Effect of End-of-Range Defects on Device Leakage in Direct Silicon Bonded (DSB) Technology

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2008, p.34-35

2008

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IEEE_Xplore

Direct Silicon Bonded (DSB) Substrate Solid Phase Epitaxy (SPE) Integration Scheme Study for High Performance Bulk CMOS

2006 International Electron Devices Meeting, 2006, p.1-4

2006

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IEEE_Xplore

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Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance

Ultrathin strained-SOI by stress balance on compliant substrates and FET performance

Buckling suppression of SiGe islands on compliant substrates

Nanopatterning of Si/SiGe electrical devices by atomic force microscopy oxidation

Study of sigma-shaped source/drain recesses for embedded-SiGe pMOSFETs

FinFETs using reverse substrate layer with improved gate capacitance characteristics for subthreshold application

Will SOI have a life for the low-power market?

Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22 nm all-last high-k/metal-gate pMOSFETs

Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22nm all-last high-k/metal-gate pMOSFETs

Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 22 nm node pMOSFETs

Rapid yield ramp using closed loop DFM and overlay process window qualification flow

Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 22nm node pMOSFETs

Punch through stop layer optimization in bulk FinFETs

Study of electron mobility on silicon with different crystalline orientations

Tunable uniaxial vs biaxial in-plane strain using compliant substrates

Performance optimization of n-MOSFETs using asymmetric interfacial oxide layer

Low leakage bulk silicon substrate based SDOI FINFETs

High-germanium-content SiGe islands formed on compliant oxide by SiGe oxidation

Advancement of maxillary anterior segment by distraction osteogenesis for severe maxillary retrusion in cleft lip and palate

Strain relaxation of silicon-germanium on compliant borophosphosilicate glass and its applications

35nm SOI-CMOS for Sub-Ambient Temperature Operation

Catalytic methanation of syngas over Ni-based catalysts with different supports

Effect of End-of-Range Defects on Device Leakage in Direct Silicon Bonded (DSB) Technology

Direct Silicon Bonded (DSB) Substrate Solid Phase Epitaxy (SPE) Integration Scheme Study for High Performance Bulk CMOS

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