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Taskflow: A Lightweight Parallel and Heterogeneous Task Graph Computing System

IEEE transactions on parallel and distributed systems, 2022-06, Vol.33 (6), p.1303-1320

2022

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Revisiting stepwise ocean oxygenation with authigenic barium enrichments in marine mudrocks

Geology (Boulder), 2021-09, Vol.49 (9), p.1059-1063

2021

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Taskflow: A General-Purpose Parallel and Heterogeneous Task Programming System

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-05, Vol.41 (5), p.1448-1452

2022

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High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-09, Vol.36 (9), p.1532-1544

2017

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Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-07, Vol.36 (7), p.1140-1152

2017

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Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks

IEEE access, 2020, Vol.8, p.25372-25382

2020

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Cell-Free Fermentation Broth of Bacillus velezensis Strain S3-1 Improves Pak Choi Nutritional Quality and Changes the Bacterial Community Structure of the Rhizosphere Soil

Frontiers in microbiology, 2020-09, Vol.11, p.2043-2043

2020

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Design for manufacturability and reliability in extreme-scaling VLSI

Science China. Information sciences, 2016-06, Vol.59 (6), p.92-114, Article 061406

2016

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Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-05, Vol.34 (5), p.726-739

2015

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Unveiling the Impacts of Sodium Hypochlorite on the Characteristics and Fouling Behaviors of Different Commercial Polyvinylidene Fluoride Hollow Fiber Membranes

Membranes (Basel), 2022-10, Vol.12 (10), p.965

2022

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Redundant Local-Loop Insertion for Unidirectional Routing

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-07, Vol.36 (7), p.1113-1125

2017

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Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection

2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, p.54-59

2019

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Concurrent pin access optimization for unidirectional routing

2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 2017, p.1-6

2017

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A Preliminary Study on Silver Isotopic Composition in Polymetallic Ore Deposits in Eastern China

Journal of earth science (Wuhan, China), 2022-02, Vol.33 (1), p.100-108

2022

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Generative Learning in VLSI Design for Manufacturability: Current Status and Future Directions

Journal of microelectronic manufacturing, 2019-12, Vol.2 (4), p.1-8

2019

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Pushing multiple patterning in sub-10nm: are we ready?

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6

2015

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GPU acceleration in VLSI back-end design: overview and case studies

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-4

Lin, Yibo

2020

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Deep Learning for Mask Synthesis and Verification: A Survey

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC), 2021, p.825-832

Lin, Yibo

2021

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Learning placement order for constructive floorplanning

Integration (Amsterdam), 2024-10, p.102293, Article 102293

2024

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High performance dummy fill insertion with coupling and uniformity constraints

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6

2015

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A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-08, p.1-1

2024

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Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-06, Vol.43 (6), p.1624-1637

2024

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Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-02, Vol.43 (2), p.641-653

2024

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Introduction to the Special Issue on Machine Learning for CAD/EDA

ACM transactions on design automation of electronic systems, 2023-03, Vol.28 (2), p.1-2, Article 14

2023

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Patterning Aware Design Optimization of Selective Etching in N5 and Beyond

2017 IEEE International Conference on Computer Design (ICCD), 2017, p.415-418

2017

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Taskflow: A Lightweight Parallel and Heterogeneous Task Graph Computing System

Revisiting stepwise ocean oxygenation with authigenic barium enrichments in marine mudrocks

Taskflow: A General-Purpose Parallel and Heterogeneous Task Programming System

High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints

Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict

Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks

Cell-Free Fermentation Broth of Bacillus velezensis Strain S3-1 Improves Pak Choi Nutritional Quality and Changes the Bacterial Community Structure of the Rhizosphere Soil

Design for manufacturability and reliability in extreme-scaling VLSI

Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography

Unveiling the Impacts of Sodium Hypochlorite on the Characteristics and Fouling Behaviors of Different Commercial Polyvinylidene Fluoride Hollow Fiber Membranes

Redundant Local-Loop Insertion for Unidirectional Routing

Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection

Concurrent pin access optimization for unidirectional routing

A Preliminary Study on Silver Isotopic Composition in Polymetallic Ore Deposits in Eastern China

Generative Learning in VLSI Design for Manufacturability: Current Status and Future Directions

Pushing multiple patterning in sub-10nm: are we ready?

GPU acceleration in VLSI back-end design: overview and case studies

Deep Learning for Mask Synthesis and Verification: A Survey

Learning placement order for constructive floorplanning

High performance dummy fill insertion with coupling and uniformity constraints

A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections

Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration

Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization

Introduction to the Special Issue on Machine Learning for CAD/EDA

Patterning Aware Design Optimization of Selective Etching in N5 and Beyond

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