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Defect structure and Fermi-level pinning of BaTiO 3 co-doped with a variable-valence acceptor (Mn) and a fixed-valence donor (Y)

Physical chemistry chemical physics : PCCP, 2012-02, Vol.14 (5), p.1642-1648

2012

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High-Performance Twin Silicon Nanowire MOSFET (TSNWFET) on Bulk Si Wafer

IEEE transactions on nanotechnology, 2008-03, Vol.7 (2), p.181-184

2008

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Investigation on hot carrier reliability of Gate-All-Around Twin Si Nanowire Field Effect Transistor

2009 IEEE International Reliability Physics Symposium, 2009, p.400-404

2009

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Characterization and Modeling of 1/ f Noise in Si-nanowire FETs: Effects of Cylindrical Geometry and Different Processing of Oxides

IEEE transactions on nanotechnology, 2011-05, Vol.10 (3), p.417-423

2011

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Twin silicon nanowire FET (TSNWFET) On SOI with 8 nm silicon nanowires and 25 nm surrounding TiN gate

2008 IEEE International SOI Conference, 2008, p.117-118

2008

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C- V Characteristics in Undoped Gate-All-Around Nanowire FET Array

IEEE electron device letters, 2011-02, Vol.32 (2), p.116-118

2011

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Characteristics of the Series Resistance Extracted From Si Nanowire FETs Using the Y -Function Technique

IEEE transactions on nanotechnology, 2010-03, Vol.9 (2), p.212-217

2010

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Temperature-Dependent Characteristics of Cylindrical Gate-All-Around Twin Silicon Nanowire MOSFETs (TSNWFETs)

IEEE electron device letters, 2007-12, Vol.28 (12), p.1129-1131

2007

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Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate

2009 Symposium on VLSI Technology, 2009, p.94-95

2009

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Investigation of nanowire size dependency on TSNWFET

2007 IEEE International Electron Devices Meeting, 2007, p.891-894

2007

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Comparison of Series Resistance and Mobility Degradation Extracted from n- and p-Type Si-Nanowire Field Effect Transistors Using the $Y$-Function Technique

Japanese Journal of Applied Physics, 2010-04, Vol.49 (4), p.04DN06-04DN06-5

2010

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Defect structure and Fermi-level pinning of BaTiO3 co-doped with a variable-valence acceptor (Mn) and a fixed-valence donor (Y)

Physical chemistry chemical physics : PCCP, 2012-02, Vol.14 (5), p.1642-1648

2012

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Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly Si channels in SOI structure

2009 Symposium on VLSI Technology, 2009, p.142-143

2009

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TSNWFET for SRAM cell application: Performance variation and process dependency

2008 Symposium on VLSI Technology, 2008, p.38-39

2008

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Fabrication and electrical characteristics of self-aligned (SA) gate-all-around (GAA) si nanowire MOSFETs (SNWFET)

2010 IEEE International Conference on Integrated Circuit Design and Technology, 2010, p.63-66

2010

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Gate-all-around Twin Silicon nanowire SONOS Memory

2007 IEEE Symposium on VLSI Technology, 2007, p.142-143

2007

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Gate-all-around single silicon nanowire MOSFET with 7 nm width for SONOS NAND flash memory

2008 Symposium on VLSI Technology, 2008, p.138-139

2008

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Defect structure and Fermi-level pinning of BaTiO sub(3) co-doped with a variable-valence acceptor (Mn) and a fixed-valence donor (Y)

Physical chemistry chemical physics : PCCP, 2012-01, Vol.14 (5), p.1642-1648

2012

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Characterization of Gate-All-Around Si-NWFET, including Rsd, cylindrical coordinate based 1/f noise and hot carrier effects

2010 IEEE International Reliability Physics Symposium, 2010, p.94-98

2010

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Experimental Investigation on Superior PMOS Performance of Uniaxial Strained ≪110≫ Silicon Nanowire Channel By Embedded SiGe Source/Drain

2007 IEEE International Electron Devices Meeting, 2007, p.899-902

2007

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Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires

2006 International Electron Devices Meeting, 2006, p.1-4

2006

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TiN/HfSiOx Gate Stack Multi-Channel Field Effect Transistor (McFET) for Sub 55nm SRAM Application

2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers, 2006, p.72-73

2006

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[Formula Omitted]-[Formula Omitted] Characteristics in Undoped Gate-All-Around Nanowire FET Array

IEEE electron device letters, 2011-02, Vol.32 (2), p.116

2011

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Characterization and Modeling of 1/[Formula Omitted] Noise in Si-nanowire FETs: Effects of Cylindrical Geometry and Different Processing of Oxides

IEEE transactions on nanotechnology, 2011-05, Vol.10 (3), p.417

2011

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Characteristics of the Series Resistance Extracted From Si Nanowire FETs Using the [Formula Omitted]-Function Technique

IEEE transactions on nanotechnology, 2010-03, Vol.9 (2), p.212

2010

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Defect structure and Fermi-level pinning of BaTiO 3 co-doped with a variable-valence acceptor (Mn) and a fixed-valence donor (Y)

High-Performance Twin Silicon Nanowire MOSFET (TSNWFET) on Bulk Si Wafer

Investigation on hot carrier reliability of Gate-All-Around Twin Si Nanowire Field Effect Transistor

Characterization and Modeling of 1/ f Noise in Si-nanowire FETs: Effects of Cylindrical Geometry and Different Processing of Oxides

Twin silicon nanowire FET (TSNWFET) On SOI with 8 nm silicon nanowires and 25 nm surrounding TiN gate

C- V Characteristics in Undoped Gate-All-Around Nanowire FET Array

Characteristics of the Series Resistance Extracted From Si Nanowire FETs Using the Y -Function Technique

Temperature-Dependent Characteristics of Cylindrical Gate-All-Around Twin Silicon Nanowire MOSFETs (TSNWFETs)

Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate

Investigation of nanowire size dependency on TSNWFET

Comparison of Series Resistance and Mobility Degradation Extracted from n- and p-Type Si-Nanowire Field Effect Transistors Using the $Y$-Function Technique

Defect structure and Fermi-level pinning of BaTiO3 co-doped with a variable-valence acceptor (Mn) and a fixed-valence donor (Y)

Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly Si channels in SOI structure

TSNWFET for SRAM cell application: Performance variation and process dependency

Fabrication and electrical characteristics of self-aligned (SA) gate-all-around (GAA) si nanowire MOSFETs (SNWFET)

Gate-all-around Twin Silicon nanowire SONOS Memory

Gate-all-around single silicon nanowire MOSFET with 7 nm width for SONOS NAND flash memory

Defect structure and Fermi-level pinning of BaTiO sub(3) co-doped with a variable-valence acceptor (Mn) and a fixed-valence donor (Y)

Characterization of Gate-All-Around Si-NWFET, including Rsd, cylindrical coordinate based 1/f noise and hot carrier effects

Experimental Investigation on Superior PMOS Performance of Uniaxial Strained ≪110≫ Silicon Nanowire Channel By Embedded SiGe Source/Drain

Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires

TiN/HfSiOx Gate Stack Multi-Channel Field Effect Transistor (McFET) for Sub 55nm SRAM Application

[Formula Omitted]-[Formula Omitted] Characteristics in Undoped Gate-All-Around Nanowire FET Array

Characterization and Modeling of 1/[Formula Omitted] Noise in Si-nanowire FETs: Effects of Cylindrical Geometry and Different Processing of Oxides

Characteristics of the Series Resistance Extracted From Si Nanowire FETs Using the [Formula Omitted]-Function Technique

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