UB Paderborn / Katalog / Suche / in CDI

Fast coding unit decision and mode selection for intra-frame coding in high-efficiency video coding

IET image processing, 2016-03, Vol.10 (3), p.215-221

2016

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Design of a 1-GSample/s 9-b double sampling track-and-hold amplifier in BiCMOS technology

International journal of circuit theory and applications, 2014-05, Vol.42 (5), p.511-528

2014

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A low distortion CMOS continuous-time common-mode feedback circuit

International journal of circuit theory and applications, 2011-12, Vol.39 (12), p.1231-1246

2011

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A High-Throughput JPEG XR Encoder

Journal of signal processing systems, 2016-11, Vol.85 (2), p.249-261

2016

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An efficient reflection invariance region-based image retrieval framework

International journal of imaging systems and technology, 2010-06, Vol.20 (2), p.155-161

2010

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A novel flash analog-to-digital converter

2008 IEEE International Symposium on Circuits and Systems, 2008, p.2250-2253

2008

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Improved edge-directed super resolution

International journal of computers & applications, 2015-10, Vol.37 (3-4), p.160-167

2015

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Power minimization for dynamically reconfigurable FPGA partitioning

ACM transactions on embedded computing systems, 2013-03, Vol.12 (1S), p.1-22

2013

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An efficient algorithm for finding the minimal-area FPGA technology mapping

ACM transactions on design automation of electronic systems, 2005-01, Vol.10 (1), p.168-186

2005

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Design of 1-GSample/s 9-b BiCMOS track-and-hold amplifier with high linear input stage

International journal of electronics, 2012-01, Vol.99 (1), p.67-78

2012

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A novel digital pixel sensor system

2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.2297-2300

2009

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A folding technique for reducing circuit complexity of flash ADC decoders

Analog integrated circuits and signal processing, 2010-05, Vol.63 (2), p.339-348

2010

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Hierarchical interconnection structures for field programmable gate arrays

IEEE transactions on very large scale integration (VLSI) systems, 1997-06, Vol.5 (2), p.186-196

1997

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Graph-theory-based simplex algorithm for VLSI layout spacing problems with multiple variable constraints

IEEE transactions on computer-aided design of integrated circuits and systems, 2001-08, Vol.20 (8), p.967-979

2001

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A Performance-Oriented Algorithm with Consideration on Communication Cost for Dynamically Reconfigurable FPGA Partitioning

ACM transactions on reconfigurable technology and systems, 2011-05, Vol.4 (2), p.1-18

2011

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An optimisation communication cost algorithm for dynamically reconfigurable FPGAs

International journal of electronics, 2010-02, Vol.97 (2), p.177-182

2010

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Low-Energy Cluster Head Selection for Clustering Communication Protocols in Wireless Sensor Network

International journal of computers & applications, 2011-01, Vol.33 (1), p.9-14

2011

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Laplacian-based H.264 intra-prediction mode decision

7th International Conference on Communications and Networking in China, 2012, p.638-641

2012

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A Performance-Driven Rotational Invariant Image Retrieval System

Journal of Information Science and Engineering, 2010-11, Vol.26 (6), p.2009-2022

2010

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Algorithms for floorplan design via rectangular dualization

IEEE transactions on computer-aided design of integrated circuits and systems, 1988-12, Vol.7 (12), p.1278-1289

1988

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BDD decomposition for mixed CMOS/PTL logic circuit synthesis

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.5649-5652 Vol. 6

2005

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Placement for the reconfigurable datapath architecture

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.1875-1878 Vol. 2

2005

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Performance-directed compaction for VLSI symbolic layouts

Computer aided design, 1995, Vol.27 (1), p.65-74

1995

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A VLSI architecture for three-step search with variable block size motion vector

The 1st IEEE Global Conference on Consumer Electronics 2012, 2012, p.628-631

2012

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Design of the ordinary differential equation solver in the Yau filtering system

Proceedings of the 2002 American Control Conference (IEEE Cat. No.CH37301), 2002, Vol.6, p.5144-5149 vol.6

2002

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Fast coding unit decision and mode selection for intra-frame coding in high-efficiency video coding

Design of a 1-GSample/s 9-b double sampling track-and-hold amplifier in BiCMOS technology

A low distortion CMOS continuous-time common-mode feedback circuit

A High-Throughput JPEG XR Encoder

An efficient reflection invariance region-based image retrieval framework

A novel flash analog-to-digital converter

Improved edge-directed super resolution

Power minimization for dynamically reconfigurable FPGA partitioning

An efficient algorithm for finding the minimal-area FPGA technology mapping

Design of 1-GSample/s 9-b BiCMOS track-and-hold amplifier with high linear input stage

A novel digital pixel sensor system

A folding technique for reducing circuit complexity of flash ADC decoders

Hierarchical interconnection structures for field programmable gate arrays

Graph-theory-based simplex algorithm for VLSI layout spacing problems with multiple variable constraints

A Performance-Oriented Algorithm with Consideration on Communication Cost for Dynamically Reconfigurable FPGA Partitioning

An optimisation communication cost algorithm for dynamically reconfigurable FPGAs

Low-Energy Cluster Head Selection for Clustering Communication Protocols in Wireless Sensor Network

Laplacian-based H.264 intra-prediction mode decision

A Performance-Driven Rotational Invariant Image Retrieval System

Algorithms for floorplan design via rectangular dualization

BDD decomposition for mixed CMOS/PTL logic circuit synthesis

Placement for the reconfigurable datapath architecture

Performance-directed compaction for VLSI symbolic layouts

A VLSI architecture for three-step search with variable block size motion vector

Design of the ordinary differential equation solver in the Yau filtering system

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