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Unipolar Arc Ignited Partial Discharge for 650-V AlGaN/GaN HEMTs during the DC Breakdown Voltage Measurement

Energies (Basel), 2022-10, Vol.15 (20), p.7608

2022

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Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection

2022 IEEE International Reliability Physics Symposium (IRPS), 2022, p.2B.3-1-2B.3-6

2022

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A Combination of Implant Shadow and Skin Effects Leading to HV Devices Failure during the ESD Event

2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2023, p.1-7

2023

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RESURF Region Variation Induced Current Crowding Effect on HV p-LDMOS

2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2023, p.1-7

2023

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Transmission Line Pulse Width Impacting on Device Performances

2023 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan), 2023, p.227-228

2023

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Bipolar Transistors' Holding Phenomena

2023 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan), 2023, p.221-222

2023

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Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection

2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.385-388

2009

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Experimental Evaluation and Device Simulation of Device Structure Influences on Latchup Immunity in High-Voltage 40-V CMOS Process

2006 IEEE International Reliability Physics Symposium Proceedings, 2006, p.140-144

2006

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Back-gate forward bias method for low-voltage CMOS digital circuits

IEEE transactions on electron devices, 1996-06, Vol.43 (6), p.904-910

1996

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ESD protection design with latchup-free immunity in 120V SOI process

2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015, p.1-2

2015

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Stacked low-voltage PMOS for high-voltage ESD protection with latchup-free immunity

2015 Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC), 2015, p.325-328

2015

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Optimization on On-Chip Surge Protection Device for USB Type-C HV Pins

2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2020, p.1-4

2020

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Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection

2015 European Conference on Circuit Theory and Design (ECCTD), 2015, p.1-4

2015

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Gate Voltages Impacting on Latch-up Measurements

2022 IEEE International Conference on Consumer Electronics - Taiwan, 2022, p.75-76

2022

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A physical model for the correlation between holding voltage and holding current in epitaxial CMOS latch-up

IEEE electron device letters, 1998-08, Vol.19 (8), p.276-278

1998

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ESD Protection for Poly Fuses

2019 41st Annual EOS/ESD Symposium (EOS/ESD), 2019, Vol.EOS-41, p.1-10

2019

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Analyzing Gate-Driven Circuit Parameters for Adding ESD Performances

2019 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2019, p.1-2

2019

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ESD simulation on GGNMOS for 40V BCD

TENCON 2010 - 2010 IEEE Region 10 Conference, 2010, p.80-83

2010

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Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008, p.61-64

2008

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Negative Triggering Current Induced the Latch-up in the Circuit without the ESD device to Power

2024 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan), 2024, p.781-782

2024

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The Effect of the P-Substrate Connection on the HBM Robustness of P-type ESD Device

2024 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2024, p.1-8

2024

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The Influence of Gate-Series-Resistor on the ESD Protection and Switching Speed for 650V GaNHEMT Circuit

2024 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2024, p.1-6

2024

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The Failure Mechanism of the Guard-Rings in Two Different Power Domains during the Latch-Up Test

2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2022, p.1-5

2022

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Study on Latchup Path between HV-LDMOS and LV-CMOS in a 0.16-μm 30-V/1.8-V BCD Technology

2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2018, p.1-6

2018

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Source-side engineering to increase holding voltage of LDMOS in a 0.5-m 16-V BCD technology to avoid latch-up failure

2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2009, p.41-44

2009

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Unipolar Arc Ignited Partial Discharge for 650-V AlGaN/GaN HEMTs during the DC Breakdown Voltage Measurement

Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection

A Combination of Implant Shadow and Skin Effects Leading to HV Devices Failure during the ESD Event

RESURF Region Variation Induced Current Crowding Effect on HV p-LDMOS

Transmission Line Pulse Width Impacting on Device Performances

Bipolar Transistors' Holding Phenomena

Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection

Experimental Evaluation and Device Simulation of Device Structure Influences on Latchup Immunity in High-Voltage 40-V CMOS Process

Back-gate forward bias method for low-voltage CMOS digital circuits

ESD protection design with latchup-free immunity in 120V SOI process

Stacked low-voltage PMOS for high-voltage ESD protection with latchup-free immunity

Optimization on On-Chip Surge Protection Device for USB Type-C HV Pins

Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection

Gate Voltages Impacting on Latch-up Measurements

A physical model for the correlation between holding voltage and holding current in epitaxial CMOS latch-up

ESD Protection for Poly Fuses

Analyzing Gate-Driven Circuit Parameters for Adding ESD Performances

ESD simulation on GGNMOS for 40V BCD

Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration

Negative Triggering Current Induced the Latch-up in the Circuit without the ESD device to Power

The Effect of the P-Substrate Connection on the HBM Robustness of P-type ESD Device

The Influence of Gate-Series-Resistor on the ESD Protection and Switching Speed for 650V GaNHEMT Circuit

The Failure Mechanism of the Guard-Rings in Two Different Power Domains during the Latch-Up Test

Study on Latchup Path between HV-LDMOS and LV-CMOS in a 0.16-μm 30-V/1.8-V BCD Technology

Source-side engineering to increase holding voltage of LDMOS in a 0.5-m 16-V BCD technology to avoid latch-up failure

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