UB Paderborn / Katalog / Suche / in CDI

Advances in sustainable nano-biochar: precursors, synthesis methods and applications

Nanoscale, 2024-01, Vol.16 (32), p.15009-15032

2024

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Embedded software optimization for MP3 decoder implemented on RISC core

IEEE transactions on consumer electronics, 2004-11, Vol.50 (4), p.1244-1249

2004

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AN OBJECT ORIENTED MODEL SCHEDULING FOR MEDIA-SOC

Journal of electronics (China), 2009, Vol.26 (2), p.244-251

2009

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DATA BYPASSING ARCHITECTURE AND CIRCUIT DESIGN FOR 32-BIT DIGITAL SIGNAL PROCESSOR

Journal of electronics (China), 2005-11, Vol.22 (6), p.640-649

2005

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Building a multi-FPGA-based emulation framework to support networks-on-chip design and verification

International journal of electronics, 2010-10, Vol.97 (10), p.1241-1262

2010

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An efficient protocol with synchronization accelerator for multi-processor embedded systems

Parallel computing, 2013-09, Vol.39 (9), p.461-474

2013

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An efficient scheduler of RTOS for multi/many-core system

Computers & electrical engineering, 2012-05, Vol.38 (3), p.785-800

2012

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A networks-on-chip architecture design space exploration – The LIB

Computers & electrical engineering, 2009-11, Vol.35 (6), p.817-836

2009

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Hierarchical motion estimation algorithms with especially low hardware costs

IEEE transactions on consumer electronics, 1998-02, Vol.44 (1), p.125-129

1998

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Numerical modeling of simultaneous hydraulic fracturing in the mode of multi-well pads

Science China. Technological sciences, 2017-02, Vol.60 (2), p.232-242

2017

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Building a multi-FPGA-based emulation framework to support networks-on-chip design and verification : Evolutionary synthesis of network-on-chip-based systems

International journal of electronics, 2010, Vol.97 (9-10), p.1241-1262

2010

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A Pseudo-Random Program Generator for Processor Functional Verification

2007 International Symposium on Integrated Circuits, 2007, p.441-444

2007

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A NoC Emulation/Verification Framework

2009 Sixth International Conference on Information Technology: New Generations, 2009, p.859-864

2009

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Optimization of the T3-induced Xenopus metamorphosis assay for detecting thyroid hormone signaling disruption of chemicals

Journal of environmental sciences (China), 2017-02, Vol.52 (2), p.314-324

2017

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RISC3202: A Software Configuration Dual-Issue/Dual-Core Microprocessor

2007 IFIP International Conference on Network and Parallel Computing Workshops (NPC 2007), 2007, p.963-968

2007

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Mathematical Model and Experiment Validation of Fluid Torque by Shear Stress under Influence of Fluid Temperature in Hydro-viscous Clutch

Chinese journal of mechanical engineering, 2014, Vol.27 (1), p.32-40

English ed., 2014

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Media Instruction Design for RISC3200

2007 International Symposium on Integrated Circuits, 2007, p.232-235

2007

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A distributed source coding for dense camera array

Proceedings 7th International Conference on Signal Processing, 2004. Proceedings. ICSP '04. 2004, 2004, Vol.1, p.819-822 vol.1

2004

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"Media processor and SoC"

Proceedings of 2005 IEEE International Workshop on VLSI Design and Video Technology, 2005, 2005, p.xxi-xxii

QingDong Yao

2005

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Hierarchical motion estimation algorithms with especially low hardware costs

Computer standards and interfaces, 1999-03, Vol.20 (6), p.453-453

1999

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A bus arbitration scheme for HDTV decoder SoC

Asia-Pacific Conference on Circuits and Systems, 2002, Vol.2, p.79-83 vol.2

2002

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Synthetic high coding for the pal luminance signal

Signal processing, 1985-01, Vol.8 (2), p.163-177

1985

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An estimation of low bound for two-dimensional image compression coding

Image Analysis Applications and Computer Graphics, 1995, p.495-496

1995

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Structure-oriented marker extraction in morphological segmentation

ICSP '98. 1998 Fourth International Conference on Signal Processing (Cat. No.98TH8344), 1998, Vol.2, p.972-973 vol.2

1998

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An easily reconfigurable simulation environment on FPGA based platform

Proceedings of 2005 IEEE International Workshop on VLSI Design and Video Technology, 2005, 2005, p.71-74

2005

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Advances in sustainable nano-biochar: precursors, synthesis methods and applications

Embedded software optimization for MP3 decoder implemented on RISC core

AN OBJECT ORIENTED MODEL SCHEDULING FOR MEDIA-SOC

DATA BYPASSING ARCHITECTURE AND CIRCUIT DESIGN FOR 32-BIT DIGITAL SIGNAL PROCESSOR

Building a multi-FPGA-based emulation framework to support networks-on-chip design and verification

An efficient protocol with synchronization accelerator for multi-processor embedded systems

An efficient scheduler of RTOS for multi/many-core system

A networks-on-chip architecture design space exploration – The LIB

Hierarchical motion estimation algorithms with especially low hardware costs

Numerical modeling of simultaneous hydraulic fracturing in the mode of multi-well pads

Building a multi-FPGA-based emulation framework to support networks-on-chip design and verification : Evolutionary synthesis of network-on-chip-based systems

A Pseudo-Random Program Generator for Processor Functional Verification

A NoC Emulation/Verification Framework

Optimization of the T3-induced Xenopus metamorphosis assay for detecting thyroid hormone signaling disruption of chemicals

RISC3202: A Software Configuration Dual-Issue/Dual-Core Microprocessor

Mathematical Model and Experiment Validation of Fluid Torque by Shear Stress under Influence of Fluid Temperature in Hydro-viscous Clutch

Media Instruction Design for RISC3200

A distributed source coding for dense camera array

"Media processor and SoC"

Hierarchical motion estimation algorithms with especially low hardware costs

A bus arbitration scheme for HDTV decoder SoC

Synthetic high coding for the pal luminance signal

An estimation of low bound for two-dimensional image compression coding

Structure-oriented marker extraction in morphological segmentation

An easily reconfigurable simulation environment on FPGA based platform

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