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The complexity of the optimal variable ordering problems of shared binary decision diagrams

Algorithms and Computation, 2005, p.389-398

2005

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Hardness of identifying the minimum ordered binary decision diagram: Special Issue: Boolean Functions and Related Problems

Discrete applied mathematics, 2000, Vol.107 (1-3), p.191-201

2000

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Redundant CORDIC methods with a constant scale factor for sine and cosine computation

IEEE transactions on computers, 1991-09, Vol.40 (9), p.989-995

1991

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Hardness of identifying the minimum ordered binary decision diagram

Discrete Applied Mathematics, 2000-12, Vol.107 (1), p.191-201

2000

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Log-depth circuits for elementary functions using residue number system

Electronics & communications in Japan. Part 3, Fundamental electronic science, 1991, Vol.74 (8), p.31-38

1991

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High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

IEEE transactions on computers, 1985-09, Vol.C-34 (9), p.789-796

1985

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Efficient initial approximation for multiplicative division and square root by a multiplication with operand modification

IEEE transactions on computers, 1997-04, Vol.46 (4), p.495-498

1997

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Size and variable ordering of OBDDs representing threshold functions

Computing and Combinatorics, 2006, p.91-100

2006

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Modular multiplication hardware algorithms with a redundant representation and their application to RSA cryptosystem

IEEE transactions on computers, 1992-07, Vol.41 (7), p.887-891

1992

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Tree-shellability of Boolean functions

Theoretical computer science, 2001, Vol.262 (1-2), p.633-647

2001

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Exponential lower bounds on the size of OBDDs representing integer division

Algorithms and Computation, 1997, p.163-172

1997

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On the size of ordered binary decision diagrams representing threshold functions

Algorithms and Computation, 2005, p.584-592

2005

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Optimizing OBDDs is still intractable for monotone functions

Lecture notes in computer science, 1998, p.625-635

1998

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Problems of relational database design

Data Base Design Techniques I, 2005, p.172-218

2005

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Design verification of a microprocessor using branching time regular temporal logic

Computer Aided Verification, 2005, p.206-219

2005

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Breadth-first manipulation of SBDD of Boolean functions for vector processing

28th ACM/IEEE Design Automation Conference, 1991, p.413-416

1991

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A file organization suitable for relational database operations

Mathematical Studies of Information Processing, 2005, p.193-227

2005

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Vectorized symbolic model checking of computation tree logic for sequential machine verification

Computer Aided Verification, 2005, p.214-224

2005

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Formal verification of speed-dependent asynchronous circuits using symbolic model checking of Branching Time Regular Temporal Logic

Computer Aided Verification, 2005, p.410-420

2005

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Square rooting by iterative multiply-additions

Information processing letters, 1996-12, Vol.60 (5), p.267-269

1996

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O(n)-depth modular exponentiation circuit algorithm

IEEE transactions on computers, 1997-06, Vol.46 (6), p.701-704, Article 701

1997

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Fault simulation for multiple faults by Boolean function manipulation

IEEE transactions on computer-aided design of integrated circuits and systems, 1994-04, Vol.13 (4), p.531-535

1994

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Description and verification of input constraints and input-output specifications of logic circuits

Systems and computers in Japan, 1987, Vol.18 (2), p.29-42

1987

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Regular temporal logic and its model checking problem

Theoretical computer science, 1992-09, Vol.103 (2), p.191-204

1992

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A square root hardware algorithm using redundant binary representation

Systems and computers in Japan, 1986, Vol.17 (11), p.30-41

1986

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The complexity of the optimal variable ordering problems of shared binary decision diagrams

Hardness of identifying the minimum ordered binary decision diagram: Special Issue: Boolean Functions and Related Problems

Redundant CORDIC methods with a constant scale factor for sine and cosine computation

Hardness of identifying the minimum ordered binary decision diagram

Log-depth circuits for elementary functions using residue number system

High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

Efficient initial approximation for multiplicative division and square root by a multiplication with operand modification

Size and variable ordering of OBDDs representing threshold functions

Modular multiplication hardware algorithms with a redundant representation and their application to RSA cryptosystem

Tree-shellability of Boolean functions

Exponential lower bounds on the size of OBDDs representing integer division

On the size of ordered binary decision diagrams representing threshold functions

Optimizing OBDDs is still intractable for monotone functions

Problems of relational database design

Design verification of a microprocessor using branching time regular temporal logic

Breadth-first manipulation of SBDD of Boolean functions for vector processing

A file organization suitable for relational database operations

Vectorized symbolic model checking of computation tree logic for sequential machine verification

Formal verification of speed-dependent asynchronous circuits using symbolic model checking of Branching Time Regular Temporal Logic

Square rooting by iterative multiply-additions

O(n)-depth modular exponentiation circuit algorithm

Fault simulation for multiple faults by Boolean function manipulation

Description and verification of input constraints and input-output specifications of logic circuits

Regular temporal logic and its model checking problem

A square root hardware algorithm using redundant binary representation

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