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Study of Local BTI Variation and its Impact on Logic Circuit and SRAM in 7 nm Fin-FET Process

2019 IEEE International Reliability Physics Symposium (IRPS), 2019, p.1-6

2019

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A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

Japanese Journal of Applied Physics, 2018-04, Vol.57 (4S), p.4

2018

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A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation

IEICE transactions on electronics, 2014, Vol.E97.C (4), p.332-341

2014

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A 3-nm FinFET 27.6-Mbit/mm 2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

IEEE journal of solid-state circuits, 2024-04, Vol.59 (4), p.1225-1234

2024

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A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures

IEEE transactions on very large scale integration (VLSI) systems, 2018-11, Vol.26 (11), p.2335-2344

2018

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A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

IEEE journal of solid-state circuits, 2024-04, Vol.59 (4), p.1225-1234

2024

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A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2

2019 Symposium on VLSI Technology, 2019, p.C248-C249

2019

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A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

IEEE journal of solid-state circuits, 2007-04, Vol.42 (4), p.820-829

2007

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A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

2023

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Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access

IEEE journal of solid-state circuits, 2009-03, Vol.44 (3), p.977-986

2009

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A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) embedded SRAM with 13.72 nW/Mbit standby power for smart IoT

2017 Symposium on VLSI Technology, 2017, p.C220-C221

2017

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28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique

IEEE transactions on very large scale integration (VLSI) systems, 2014-03, Vol.22 (3), p.575-584

2014

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A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.180-191

2008

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A Robust SOI SRAM Architecture by using Advanced ABC technology for 32nm node and beyond LSTP devices

2007 IEEE Symposium on VLSI Technology, 2007, p.78-79

2007

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A dynamic/static SRAM power management scheme for DVFS and AVS in advanced automotive infotainment SoCs

2016 IEEE Symposium on VLSI Technology, 2016, p.1-2

2016

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A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues

IEEE journal of solid-state circuits, 2008-04, Vol.43 (4), p.938-945

2008

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13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, p.234-235

2014

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Silicon measurements of characteristics for passgate/pull-down/pull-up MOSs and search MOS in a 28 nm HKMG TCAM bitcell

Proceedings of the 2015 International Conference on Microelectronic Test Structures, 2015, p.200-203

2015

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A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010, p.356-357

2010

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A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.96-108

2008

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A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs

2012 IEEE International Solid-State Circuits Conference, 2012, p.236-238

2012

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A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues

2012 IEEE 21st Asian Test Symposium, 2012, p.246-251

2012

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A stable chip-ID generating physical uncloneable function using random address errors in SRAM

2012 IEEE International SOC Conference, 2012, p.143-147

2012

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A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved Electromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line Amplifier

2020 IEEE Symposium on VLSI Circuits, 2020, p.1-2

2020

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Study of Local BTI Variation and its Impact on Logic Circuit and SRAM in 7 nm Fin-FET Process

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation

A 3-nm FinFET 27.6-Mbit/mm 2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures

A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction

A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking

Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access

A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) embedded SRAM with 13.72 nW/Mbit standby power for smart IoT

28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

A Robust SOI SRAM Architecture by using Advanced ABC technology for 32nm node and beyond LSTP devices

A dynamic/static SRAM power management scheme for DVFS and AVS in advanced automotive infotainment SoCs

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues

13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists

Silicon measurements of characteristics for passgate/pull-down/pull-up MOSs and search MOS in a 28 nm HKMG TCAM bitcell

A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs

A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues

A stable chip-ID generating physical uncloneable function using random address errors in SRAM

A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved Electromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line Amplifier

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