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Complementary Metal–Oxide–Semiconductor Compatible 2D Layered Film‐Based Gas Sensors by Floating‐Gate Coupling Effect

Advanced functional materials, 2022-03, Vol.32 (13), p.n/a

2022

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Evaluation of stability and robustness of poly-Si resistors with different dopant concentrations

Japanese Journal of Applied Physics, 2022-05, Vol.61 (SC), p.SC1060

2022

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Polarity and Patterning Effect on Plasma Charging Levels by Metal-Gate Coupled Recorder Arrays

IEEE transactions on electron devices, 2022-12, Vol.69 (12), p.6971-6976

2022

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High-Density Embedded 3-D Stackable Via RRAM in 16-nm FinFET CMOS Logic Process

IEEE transactions on electron devices, 2024-06, Vol.71 (6), p.3614-3619

2024

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On-Wafer FinFET-Based 3-D E-Beam Detector Cube for In Situ Monitoring of Advanced Lithography Processes Beyond 5 nm

IEEE transactions on electron devices, 2024-06, Vol.71 (6), p.3739-3745

2024

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Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors

IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.203-215

2020

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CMOS-Compatible Embedded Artificial Synaptic Device (eASD) for Neuromorphic Computing and AI Applications

IEEE transactions on electron devices, 2024-02, Vol.71 (2), p.1-7

2024

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A New High Density 3D Stackable Via RRAM for Computing-in-Memory SOC Applications

IEEE transactions on electron devices, 2024-04, Vol.71 (4), p.2399-2403

2024

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Memory-Logic Hybrid Gate With 3-D Stackable Complementary Latches

IEEE transactions on electron devices, 2020-08, Vol.67 (8), p.3109-3114

2020

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A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.494-496

2018

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A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors

IEEE journal of solid-state circuits, 2017-08, Vol.52 (8), p.2194-2207

2017

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3-D Stackable Offset-Via Antifuse by Cu BEOL Process in Advanced CMOS Technologies

IEEE transactions on electron devices, 2023-12, Vol.70 (12), p.6273-6278

2023

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4K Detectors Array for On-Wafer EUV Imaging in Lithography Control Beyond 5-nm Node

IEEE transactions on electron devices, 2023-11, Vol.70 (11), p.5713-5719

2023

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Multilevel Fully Logic-Compatible Latch Array for Computing-in-Memory

IEEE transactions on electron devices, 2023-04, Vol.70 (4), p.2001-2008

2023

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A Contact-Resistive Random-Access-Memory-Based True Random Number Generator

IEEE electron device letters, 2012-08, Vol.33 (8), p.1108-1110

2012

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On-Wafer Electron Beam Detectors by Floating-Gate FinFET Technologies

IEEE transactions on electron devices, 2021-09, Vol.68 (9), p.4651-4655

2021

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Multifunctional Ion‐Sensitive Floating Gate Fin Field‐Effect Transistor with Three‐Dimensional Nanoseaweed Structure by Glancing Angle Deposition Technology

Small (Weinheim an der Bergstrasse, Germany), 2022-02, Vol.18 (5), p.e2104168-n/a

2022

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A Study of the Variability in Contact Resistive Random Access Memory by Stochastic Vacancy Model

Nanoscale research letters, 2018-07, Vol.13 (1), p.213-10, Article 213

2018

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Embedded Micro-detectors for EUV Exposure Control in FinFET CMOS Technology

Nanoscale research letters, 2022-01, Vol.17 (1), p.5-5, Article 5

2022

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Wafer-Level Mapping of Plasma-Induced Charging Effect by On-Chip In Situ Recorders in FinFET Technologies

IEEE transactions on electron devices, 2016-06, Vol.63 (6), p.2497-2502

2016

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An Early Detection Circuit for Endurance Enhancement of Backfilled Contact Resistive Random Access Memory Array

Nanoscale research letters, 2021-07, Vol.16 (1), p.114-114, Article 114

2021

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Test Pattern Design for Plasma Induced Damage on Inter-Metal Dielectric in FinFET Cu BEOL Processes

Nanoscale research letters, 2020-05, Vol.15 (1), p.96-96, Article 96

2020

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RTN and Annealing Related to Stress and Temperature in FIND RRAM Array

Nanoscale research letters, 2019-01, Vol.14 (1), p.12-12, Article 12

2019

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High-density via RRAM cell with multi-level setting by current compliance circuits

Discover nano, 2024-03, Vol.19 (1), p.54-54, Article 54

2024

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A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation

IEEE journal of solid-state circuits, 2019-02, Vol.54 (2), p.584-595

2019

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Complementary Metal–Oxide–Semiconductor Compatible 2D Layered Film‐Based Gas Sensors by Floating‐Gate Coupling Effect

Evaluation of stability and robustness of poly-Si resistors with different dopant concentrations

Polarity and Patterning Effect on Plasma Charging Levels by Metal-Gate Coupled Recorder Arrays

High-Density Embedded 3-D Stackable Via RRAM in 16-nm FinFET CMOS Logic Process

On-Wafer FinFET-Based 3-D E-Beam Detector Cube for In Situ Monitoring of Advanced Lithography Processes Beyond 5 nm

Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors

CMOS-Compatible Embedded Artificial Synaptic Device (eASD) for Neuromorphic Computing and AI Applications

A New High Density 3D Stackable Via RRAM for Computing-in-Memory SOC Applications

Memory-Logic Hybrid Gate With 3-D Stackable Complementary Latches

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors

A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors

3-D Stackable Offset-Via Antifuse by Cu BEOL Process in Advanced CMOS Technologies

4K Detectors Array for On-Wafer EUV Imaging in Lithography Control Beyond 5-nm Node

Multilevel Fully Logic-Compatible Latch Array for Computing-in-Memory

A Contact-Resistive Random-Access-Memory-Based True Random Number Generator

On-Wafer Electron Beam Detectors by Floating-Gate FinFET Technologies

Multifunctional Ion‐Sensitive Floating Gate Fin Field‐Effect Transistor with Three‐Dimensional Nanoseaweed Structure by Glancing Angle Deposition Technology

A Study of the Variability in Contact Resistive Random Access Memory by Stochastic Vacancy Model

Embedded Micro-detectors for EUV Exposure Control in FinFET CMOS Technology

Wafer-Level Mapping of Plasma-Induced Charging Effect by On-Chip In Situ Recorders in FinFET Technologies

An Early Detection Circuit for Endurance Enhancement of Backfilled Contact Resistive Random Access Memory Array

Test Pattern Design for Plasma Induced Damage on Inter-Metal Dielectric in FinFET Cu BEOL Processes

RTN and Annealing Related to Stress and Temperature in FIND RRAM Array

High-density via RRAM cell with multi-level setting by current compliance circuits

A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation

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