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High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m )

IEEE transactions on industrial electronics (1982), 2017-01, Vol.64 (1), p.727-738

2017

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Low power adiabatic logic based on FinFETs

Science China. Information sciences, 2014-02, Vol.57 (2), p.188-200

2014

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Improving DFA attacks on AES with unknown and random faults

Science China. Information sciences, 2017-04, Vol.60 (4), p.162-175, Article 042401

2017

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Key characterization factors of accurate power modeling for FinFET circuits

Science China. Information sciences, 2015-02, Vol.58 (2), p.1-13

2015

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Reliability evaluation of high-performance, low-power FinFET standard cells based on mixed RBB/FBB technique

Journal of semiconductors, 2017-04, Vol.38 (4), p.44005

2017

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Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs

Science China. Information sciences, 2014-04, Vol.57 (4), p.269-281

2014

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Multimodal Affective States Recognition Based on Multiscale CNNs and Biologically Inspired Decision Fusion Model

IEEE transactions on affective computing, 2023-04, Vol.14 (2), p.1391-1403

2023

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A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2021-07, Vol.68 (7), p.2655-2659

2021

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Employing the mixed FBB/RBB in the design of FinFET logic gates

2015 IEEE 11th International Conference on ASIC (ASICON), 2015, p.1-4

2015

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A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications

2015 IEEE 11th International Conference on ASIC (ASICON), 2015, p.1-4

2015

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ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator

IEEE transactions on very large scale integration (VLSI) systems, 2022-11, Vol.30 (11), p.1631-1641

2022

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Digital OFDM transmitter architecture and FPGA design

2009 IEEE 8th International Conference on ASIC, 2009, p.477-480

2009

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High-speed constant-time division module for Elliptic Curve Cryptography based on GF(2m)

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, p.818-821

2014

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All-digital synchronous 2 × time-difference amplifier based on time register

Electronics letters, 2017-08, Vol.53 (16), p.1102-1104

2017

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Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2018-10, Vol.26 (10), p.1922-1929

2018

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A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs

2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.129-132

2013

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A Low Power ROIC with Extended Counting ADC Based on Circuit Noise Analysis for Sensor Arrays in IoT System

Journal of sensors, 2022-10, Vol.2022, p.1-12

2022

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A New Method for Futures Price Trends Forecasting Based on BPNN and Structuring Data

IEICE Transactions on Information and Systems, 2019/09/01, Vol.E102.D(9), pp.1882-1886

2019

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A JTAG-based configuration circuit applied in SerDes chip

2011 9th IEEE International Conference on ASIC, 2011, p.707-710

2011

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A low-noise high-linearity interface ASIC for MEMS gyroscopes

Journal of semiconductors, 2013-12, Vol.34 (12), p.109-114

方然鲁文高王冠男陶婷婷张雅聪陈中建于敦山

2013

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Designing a 3D Graphics Processor for Mobile Applications

2019 IEEE 13th International Conference on ASIC (ASICON), 2019, p.1-4

2019

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An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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A parallel intra prediction architecture for H.264 video decoding

2009 IEEE 8th International Conference on ASIC, 2009, p.859-862

2009

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Low Power Readout Integrated Circuit with PFM-based ADCs Employing Residue Quantization for Uncooled Infrared Imagers

2021 IEEE 14th International Conference on ASIC (ASICON), 2021, p.1-4

2021

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Mixed optimization method in design of FC-2

2009 IEEE 8th International Conference on ASIC, 2009, p.113-116

2009

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High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m )

Low power adiabatic logic based on FinFETs

Improving DFA attacks on AES with unknown and random faults

Key characterization factors of accurate power modeling for FinFET circuits

Reliability evaluation of high-performance, low-power FinFET standard cells based on mixed RBB/FBB technique

Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs

Multimodal Affective States Recognition Based on Multiscale CNNs and Biologically Inspired Decision Fusion Model

A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS

Employing the mixed FBB/RBB in the design of FinFET logic gates

A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications

ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator

Digital OFDM transmitter architecture and FPGA design

High-speed constant-time division module for Elliptic Curve Cryptography based on GF(2m)

All-digital synchronous 2 × time-difference amplifier based on time register

Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits

A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs

A Low Power ROIC with Extended Counting ADC Based on Circuit Noise Analysis for Sensor Arrays in IoT System

A New Method for Futures Price Trends Forecasting Based on BPNN and Structuring Data

A JTAG-based configuration circuit applied in SerDes chip

A low-noise high-linearity interface ASIC for MEMS gyroscopes

Designing a 3D Graphics Processor for Mobile Applications

An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow

A parallel intra prediction architecture for H.264 video decoding

Low Power Readout Integrated Circuit with PFM-based ADCs Employing Residue Quantization for Uncooled Infrared Imagers

Mixed optimization method in design of FC-2

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