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Post-lockdown abatement of COVID-19 by fast periodic switching

PLoS computational biology, 2021-01, Vol.17 (1), p.e1008604-e1008604

2021

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Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network

IEEE transactions on industrial electronics (1982), 2011-08, Vol.58 (8), p.3701-3716

2011

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LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference

IEEE transactions on computers, 2020-12, Vol.69 (12), p.1795-1808

2020

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Verification and Fault Injection Platform Based on MTB Stimulus Generation Method for L2 Deep Market Quote Decoder

IEEE access, 2024, Vol.12, p.54272-54284

2024

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Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability

IEEE transactions on very large scale integration (VLSI) systems, 2013-12, Vol.21 (12), p.2307-2320

2013

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Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going

ACM computing surveys, 2019-05, Vol.52 (2), p.1-39, Article 40

2019

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FPGA Architecture Optimization Using Geometric Programming

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-08, Vol.29 (8), p.1163-1176

2010

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Field-Programmable Logic and Applications: 7th International Workshop, FPL '97 London, UK, September 1–3, 1997 Proceedings

1997

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Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs

IEEE transactions on very large scale integration (VLSI) systems, 2010-03, Vol.18 (3), p.436-449

2010

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Field Programmable Logic and Application: 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003 Proceedings

2003

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Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs

Journal of signal processing systems, 2008-04, Vol.51 (1), p.3-21

2008

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Context-based image acquisition from memory in digital systems

Journal of real-time image processing, 2019-08, Vol.16 (4), p.1057-1076

2019

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Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study

IEEE transactions on computers, 2010-04, Vol.59 (4), p.433-448

2010

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CypherDB: A Novel Architecture for Outsourcing Secure Database Processing

IEEE transactions on cloud computing, 2018-04, Vol.6 (2), p.372-386

2018

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Affective Level Video Segmentation by Utilizing the Pleasure-Arousal-Dominance Information

IEEE transactions on multimedia, 2008-11, Vol.10 (7), p.1325-1341

2008

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Globally Asynchronous Locally Synchronous FPGA Architectures

Field Programmable Logic and Application, 2003, p.355-364

2003

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Non-uniform Segmentation for Hardware Function Evaluation

Field Programmable Logic and Application, 2003, p.796-807

2003

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High-level power and performance estimation of FPGA-based soft processors and its application to design space exploration

Journal of systems architecture, 2013-11, Vol.59 (10), p.1144-1156

2013

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Wave-pipelined intra-chip signaling for on-FPGA communications

Integration (Amsterdam), 2010-04, Vol.43 (2), p.188-201

2010

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Power Characterisation for Fine-Grain Reconfigurable Fabrics

International Journal of Reconfigurable Computing, 2010-01, Vol.2010 (2010), p.1-9

2010

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Self-Measurement of Combinatorial Circuit Delays in FPGAs

ACM transactions on reconfigurable technology and systems, 2009-06, Vol.2 (2), p.1-22

2009

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Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems

ACM transactions on reconfigurable technology and systems, 2015-01, Vol.7 (4), p.1-17

2015

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VPR: a new packing, placement and routing tool for FPGA research

Field-Programmable Logic and Applications, 2005, p.213-222

2005

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Benchmarking and evaluating reconfigurable architectures targeting the mobile domain

ACM transactions on design automation of electronic systems, 2010-02, Vol.15 (2), p.1-24

2010

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Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices

IEEE transactions on very large scale integration (VLSI) systems, 2008-06, Vol.16 (6), p.733-744

2008

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Post-lockdown abatement of COVID-19 by fast periodic switching

Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network

LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference

Verification and Fault Injection Platform Based on MTB Stimulus Generation Method for L2 Deep Market Quote Decoder

Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability

Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going

FPGA Architecture Optimization Using Geometric Programming

Field-Programmable Logic and Applications: 7th International Workshop, FPL '97 London, UK, September 1–3, 1997 Proceedings

Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs

Field Programmable Logic and Application: 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003 Proceedings

Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs

Context-based image acquisition from memory in digital systems

Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study

CypherDB: A Novel Architecture for Outsourcing Secure Database Processing

Affective Level Video Segmentation by Utilizing the Pleasure-Arousal-Dominance Information

Globally Asynchronous Locally Synchronous FPGA Architectures

Non-uniform Segmentation for Hardware Function Evaluation

High-level power and performance estimation of FPGA-based soft processors and its application to design space exploration

Wave-pipelined intra-chip signaling for on-FPGA communications

Power Characterisation for Fine-Grain Reconfigurable Fabrics

Self-Measurement of Combinatorial Circuit Delays in FPGAs

Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems

VPR: a new packing, placement and routing tool for FPGA research

Benchmarking and evaluating reconfigurable architectures targeting the mobile domain

Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices

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