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Frequency-independent equivalent-circuit model for on-chip spiral inductors

IEEE journal of solid-state circuits, 2003-03, Vol.38 (3), p.419-426

2003

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Sub-50 nm P-channel FinFET

IEEE transactions on electron devices, 2001-05, Vol.48 (5), p.880-886

2001

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Switch-factor based loop RLC modeling for efficient timing analysis

IEEE transactions on very large scale integration (VLSI) systems, 2005-09, Vol.13 (9), p.1072-1078

2005

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Loop-based interconnect modeling and optimization approach for multigigahertz clock network design

IEEE journal of solid-state circuits, 2003-03, Vol.38 (3), p.457-463

2003

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Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design

IEEE transactions on very large scale integration (VLSI) systems, 2005-01, Vol.13 (1), p.158-162

2005

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Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion

IEEE transactions on very large scale integration (VLSI) systems, 2002-12, Vol.10 (6), p.799-805

2002

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Improved a priori interconnect predictions and technology extrapolation in the GTX system

IEEE transactions on very large scale integration (VLSI) systems, 2003-02, Vol.11 (1), p.3-14

2003

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Frequency-independent equivalent circuit model for on-chip spiral inductors

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285), 2002, p.217-220

2002

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Loop-based interconnect modeling and optimization approach for multi-GHz clock network design

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285), 2002, p.19-22

2002

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A comparison of hydrogen and deuterium plasma treatment effects on polysilicon TFT performance and dc reliability

IEEE electron device letters, 1999-08, Vol.20 (8), p.387-389

1999

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FinFET-a quasi-planar double-gate MOSFET

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), 2001, p.118-119

2001

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Effects of global interconnect optimizations on performance estimation of deep submicron design

Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design, 2000, p.56-61

2000

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Modeling and design optimization of multi-GHz IC interconnects

Huang, Xuejue

2002

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Modeling and hardware correlation of power distribution networks for multi-gigabit designs

2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546), 2004, Vol.2, p.1759-1765 Vol.2

2004

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Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design

15th Annual IEEE International ASIC/SOC Conference, 2002, p.438-442

2002

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Improved a priori interconnect predictions and technology extrapolation in the GTX system : System-level interconnect prediction (SLIP)

IEEE transactions on very large scale integration (VLSI) systems, 2003, Vol.11 (1), p.3-14

2003

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Analytical performance models for RLC interconnects and application to clock optimization

15th Annual IEEE International ASIC/SOC Conference, 2002, p.353-357

2002

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Effective on-chip inductance modeling for multiple signal lines and application on repeater insertion

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design, 2001, p.185-190

2001

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Inductance: implications and solutions for high-speed digital circuits - clock distribution

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Vol.2, p.558-562

2002

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Improved DC Reliability of Polysilicon Thin-Film Transistors with Deuterium Plasma Treatment

SID International Symposium Digest of technical papers, 1999-05, Vol.30 (1), p.398-401

1999

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Switch-factor based loop RLC modeling for efficient timing analysis

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486), 2003, p.848-853

2003

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Power distribution analysis methodology for a multi-gigabit I/O interface

Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710), 2003, p.141-144

2003

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Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis

International Conference on Computer Aided Design: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design; 09-13 Nov. 2003, 2003, p.848-848

2003

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Effects of global interconnect optimizations on performance estimation of deep submicron design

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, 2000, p.56-61

2000

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RLC signal integrity analysis of high-speed global interconnects [CMOS]

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138), 2000, p.731-734

2000

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Frequency-independent equivalent-circuit model for on-chip spiral inductors

Sub-50 nm P-channel FinFET

Switch-factor based loop RLC modeling for efficient timing analysis

Loop-based interconnect modeling and optimization approach for multigigahertz clock network design

Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design

Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion

Improved a priori interconnect predictions and technology extrapolation in the GTX system

Frequency-independent equivalent circuit model for on-chip spiral inductors

Loop-based interconnect modeling and optimization approach for multi-GHz clock network design

A comparison of hydrogen and deuterium plasma treatment effects on polysilicon TFT performance and dc reliability

FinFET-a quasi-planar double-gate MOSFET

Effects of global interconnect optimizations on performance estimation of deep submicron design

Modeling and design optimization of multi-GHz IC interconnects

Modeling and hardware correlation of power distribution networks for multi-gigabit designs

Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design

Improved a priori interconnect predictions and technology extrapolation in the GTX system : System-level interconnect prediction (SLIP)

Analytical performance models for RLC interconnects and application to clock optimization

Effective on-chip inductance modeling for multiple signal lines and application on repeater insertion

Inductance: implications and solutions for high-speed digital circuits - clock distribution

Improved DC Reliability of Polysilicon Thin-Film Transistors with Deuterium Plasma Treatment

Switch-factor based loop RLC modeling for efficient timing analysis

Power distribution analysis methodology for a multi-gigabit I/O interface

Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis

Effects of global interconnect optimizations on performance estimation of deep submicron design

RLC signal integrity analysis of high-speed global interconnects [CMOS]

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