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A 100-Mhz Bandwidth 80-dB Dynamic Range Continuous-Time Delta-Sigma Modulator with a 2.4-Ghz Clock Rate

Nanoscale research letters, 2020-03, Vol.15 (1), p.58-58, Article 58

2020

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A Low-Power Low-Cost On-Chip Digital Background Calibration for Pipelined ADCs

IEEE transactions on very large scale integration (VLSI) systems, 2019-11, Vol.27 (11), p.2568-2574

2019

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A Solution for Ultra-Low Bit-Error-Rate Interface of Superconductor-Semiconductor by Using an Error-Correction-Code Encoder

IEEE transactions on applied superconductivity, 2019-08, Vol.29 (5), p.1-4

2019

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High-Speed Demonstration of Bit-Serial Floating-Point Adders and Multipliers Using Single-Flux-Quantum Circuits

IEEE transactions on applied superconductivity, 2015-06, Vol.25 (3), p.1-6

2015

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Demonstration of Bit-Serial SFQ-Based Computing for Integer Iteration Algorithms

IEEE transactions on applied superconductivity, 2015-06, Vol.25 (3), p.1-4

2015

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A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC

IEEE journal of solid-state circuits, 2021-09, Vol.56 (9), p.2680-2690

2021

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A low-power on-chip calibration technique for pipelined ADCs

2017 IEEE 12th International Conference on ASIC (ASICON), 2017, p.612-615

2017

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Optical Neural Network With Complementary Decomposition to Overcome the Phase Insensitive Constrains

IEEE journal of selected topics in quantum electronics, 2023-03, Vol.29 (2: Optical Computing), p.1-8

2023

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A Novel Two-Stage Timing Mismatch Calibration Technique for Time-Interleaved ADCs

IEEE transactions on very large scale integration (VLSI) systems, 2023-06, Vol.31 (6), p.1-5

2023

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DBP: Distributed Power Budgeting for Many-Core Systems in Dark Silicon

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-12, Vol.41 (12), p.5727-5731

2022

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A Three-Stage Comparator and Its Modified Version With Fast Speed and Low Kickback

IEEE transactions on very large scale integration (VLSI) systems, 2021-07, Vol.29 (7), p.1485-1489

2021

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A 8.2-pW 2.4-pA Current Reference Operating at 0.5 V With No Amplifiers or Resistors

IEEE transactions on circuits and systems. II, Express briefs, 2020-07, Vol.67 (7), p.1204-1208

2020

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Low-Power, Low-Noise Edge-Race Comparator for SAR ADCs

IEEE transactions on very large scale integration (VLSI) systems, 2020-12, Vol.28 (12), p.2699-2707

2020

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A Novel NN-Based Fast-Convergence Background Calibration for Timing Mismatch in TI ADCs

IEEE transactions on circuits and systems. II, Express briefs, 2024-10, p.1-1

2024

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A Novel Calibration Algorithm for ADCs Based on Inverse Mapping by Neural Network

IEEE transactions on circuits and systems. II, Express briefs, 2024-07, Vol.71 (7), p.3283-3287

2024

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Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process

IEICE transactions on electronics, 2014, Vol.E97.C (3), p.188-193

2014

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A Timing Mismatch Background Calibration Algorithm With Improved Accuracy

IEEE transactions on very large scale integration (VLSI) systems, 2021-08, Vol.29 (8), p.1591-1595

2021

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A New Artificial Neural Network-Based Calibration Mechanism for ADCs: A Time-Interleaved ADC Case Study

IEEE transactions on very large scale integration (VLSI) systems, 2024-07, Vol.32 (7), p.1184-1194

2024

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Digital Background Calibration Techniques for Interstage Gain Error and Nonlinearity in Pipelined ADCs

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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Evolution Strategy and Controlled Residual Convolutional Neural Networks for ADC Calibration in the Absence of Ground Truth

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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A Neural Network Based Calibration Technique for TI-ADCs with Derivative Information

2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5

2023

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A Timing Mismatch Background Calibration Technique with High-Precision Skew Estimation

2021 IEEE 14th International Conference on ASIC (ASICON), 2021, p.1-4

2021

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A Back-Gate-Input Clocked Comparator with Improved Speed and Reduced Noise in 22-nm SOI CMOS

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, p.1-5

2021

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A Convolutional Neural Network Based Calibration Scheme for Pipelined ADC

2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5

2023

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A Bootstrapped Switch with Accelerated Rising Speed and Reduced On-Resistance

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, p.1-5

2021

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A 100-Mhz Bandwidth 80-dB Dynamic Range Continuous-Time Delta-Sigma Modulator with a 2.4-Ghz Clock Rate

A Low-Power Low-Cost On-Chip Digital Background Calibration for Pipelined ADCs

A Solution for Ultra-Low Bit-Error-Rate Interface of Superconductor-Semiconductor by Using an Error-Correction-Code Encoder

High-Speed Demonstration of Bit-Serial Floating-Point Adders and Multipliers Using Single-Flux-Quantum Circuits

Demonstration of Bit-Serial SFQ-Based Computing for Integer Iteration Algorithms

A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC

A low-power on-chip calibration technique for pipelined ADCs

Optical Neural Network With Complementary Decomposition to Overcome the Phase Insensitive Constrains

A Novel Two-Stage Timing Mismatch Calibration Technique for Time-Interleaved ADCs

DBP: Distributed Power Budgeting for Many-Core Systems in Dark Silicon

A Three-Stage Comparator and Its Modified Version With Fast Speed and Low Kickback

A 8.2-pW 2.4-pA Current Reference Operating at 0.5 V With No Amplifiers or Resistors

Low-Power, Low-Noise Edge-Race Comparator for SAR ADCs

A Novel NN-Based Fast-Convergence Background Calibration for Timing Mismatch in TI ADCs

A Novel Calibration Algorithm for ADCs Based on Inverse Mapping by Neural Network

Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process

A Timing Mismatch Background Calibration Algorithm With Improved Accuracy

A New Artificial Neural Network-Based Calibration Mechanism for ADCs: A Time-Interleaved ADC Case Study

Digital Background Calibration Techniques for Interstage Gain Error and Nonlinearity in Pipelined ADCs

Evolution Strategy and Controlled Residual Convolutional Neural Networks for ADC Calibration in the Absence of Ground Truth

A Neural Network Based Calibration Technique for TI-ADCs with Derivative Information

A Timing Mismatch Background Calibration Technique with High-Precision Skew Estimation

A Back-Gate-Input Clocked Comparator with Improved Speed and Reduced Noise in 22-nm SOI CMOS

A Convolutional Neural Network Based Calibration Scheme for Pipelined ADC

A Bootstrapped Switch with Accelerated Rising Speed and Reduced On-Resistance

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