UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

High Precision Low Complexity Matrix Inversion Based on Newton Iteration for Data Detection in the Massive MIMO

IEEE communications letters, 2016-03, Vol.20 (3), p.490-493

2016

Volltextzugriff (PDF)

Automatic Modulation Classification for MASK, MPSK, and MQAM Signals Based on Hierarchical Self-Organizing Map

Sensors (Basel, Switzerland), 2022-08, Vol.22 (17), p.6449

2022

Volltextzugriff (PDF)

Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router

IEEE transactions on very large scale integration (VLSI) systems, 2013-06, Vol.21 (6), p.1053-1066

2013

Volltextzugriff (PDF)

Efficient MIMO Preprocessor With Sorting-Relaxed QR Decomposition and Modified Greedy LLL Algorithm

IEEE access, 2020, Vol.8, p.54085-54099

2020

Volltextzugriff (PDF)

Low latency group‐sorted QR decomposition algorithm for larger‐scale MIMO systems

IET communications, 2021-07, Vol.15 (12), p.1548-1560

2021

Volltextzugriff (PDF)

Hardware Architecture Based on Parallel Tiled QRD Algorithm for Future MIMO Systems

IEEE transactions on very large scale integration (VLSI) systems, 2017-05, Vol.25 (5), p.1714-1724

2017

Volltextzugriff (PDF)

High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Symmetry (Basel), 2021-04, Vol.13 (4), p.700

2021

Volltextzugriff (PDF)

A Novel Architecture to Eliminate Bottlenecks in a Parallel Tiled QRD Algorithm for Future MIMO Systems

IEEE transactions on circuits and systems. II, Express briefs, 2017-01, Vol.64 (1), p.26-30

2017

Volltextzugriff (PDF)

An Improved Concatenation Scheme of BCH-Polar Codes With Low-Latency Decoding Architecture

IEEE access, 2019, Vol.7, p.95867-95877

2019

Volltextzugriff (PDF)

An Area-Efficient Hybrid Polar Decoder with Pipelined Architecture

IEEE access, 2020-01, Vol.8, p.1-1

2020

Volltextzugriff (PDF)

Area-Efficient Parallel Reconfigurable Stream Processor for Symmetric Cryptograph

IEEE access, 2021, Vol.9, p.28377-28392

2021

Volltextzugriff (PDF)

Deep learning-aided high-precision data detection for massive MU-MIMO systems

MATEC Web of Conferences, 2021, Vol.336, p.4007

2021

Volltextzugriff (PDF)

A Flexible Divide-and-Conquer MPSoC Architecture for MIMO Interference Cancellation

IEEE transactions on very large scale integration (VLSI) systems, 2017-10, Vol.25 (10), p.2789-2802

2017

Volltextzugriff (PDF)

Approximate iteration detection and precoding in massive MIMO

China communications, 2018-05, Vol.15 (5), p.183-196

2018

Volltextzugriff (PDF)

Algorithm and Architecture for Path Metric Aided Bit-Flipping Decoding of Polar Codes

2019 IEEE Wireless Communications and Networking Conference (WCNC), 2019, p.1-6

2019

Volltextzugriff (PDF)

Architecture and Implementation of a Reduced EPIC Processor

IEICE Transactions on Information and Systems, 2013/01/01, Vol.E96.D(1), pp.9-18

2013

Volltextzugriff (PDF)

Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

Journal of Electrical and Computer Engineering, 2015-01, Vol.2015 (2015), p.658-673

2015

Volltextzugriff (PDF)

Fei Teng 64 Stream Processing System: Architecture, Compiler, and Programming

IEEE transactions on parallel and distributed systems, 2009-08, Vol.20 (8), p.1142-1157

2009

Volltextzugriff (PDF)

Accelerating FDTD simulation of microwave pulse coupling into narrow slots on the Intel MIC architecture

2015 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), 2015, p.263-268

2015

Volltextzugriff (PDF)

FPGA Implementation for the Sigmoid with Piecewise Linear Fitting Method Based on Curvature Analysis

Electronics (Basel), 2022-05, Vol.11 (9), p.1365

2022

Volltextzugriff (PDF)

An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors

Advances in Computer Systems Architecture, 2006, p.588-594

2006

Volltextzugriff (PDF)

Approximate iteration detection with iterative refinement in massive MIMO systems

IET communications, 2017-05, Vol.11 (7), p.1152-1157

2017

Volltextzugriff (PDF)

A model for energy quantization of single-electron transistor below 10nm

2011 9th IEEE International Conference on ASIC, 2011, p.531-534

2011

Volltextzugriff (PDF)

Locality based warp scheduling in GPGPUs

Future generation computer systems, 2018-05, Vol.82, p.520-527

2018

Volltextzugriff (PDF)

Practical AMC model based on SAE with various optimisation methods under different noise environments

IET communications, 2020-12, Vol.14 (22), p.4081-4088

2020

Volltextzugriff (PDF)

1 – 25 von 105

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(57)
Mit Volltextzugriff
(84)

Publikationsform

Sprache

Englisch
(104)
Chinesisch
(1)

Erscheinungsjahr

n.n

Thema

Science & Technology
(70)
Technology
(58)
Computer Science
(36)
Engineering
(34)
Engineering, Electrical & Electronic
(29)
Hardware
(21)
Computer Architecture
(18)
Algorithms
(17)
Computer Science, Hardware & Architecture
(17)
Computer Science, Theory & Methods
(15)
Computer Science, Information Systems
(13)
Telecommunications
(13)
Mimo
(10)
Algorithm Design And Analysis
(9)
Architecture
(8)
Computer Simulation
(8)
Graphics Processing Units
(8)
Humans
(7)
Kinases
(7)
Life Sciences & Biomedicine
(7)

15 weitere anzeigen...

Weniger anzeigen...

Neu hinzugefügt

... seit 30 Tagen
(1)

Menü

Weitere Dienste

Einstellungen

High Precision Low Complexity Matrix Inversion Based on Newton Iteration for Data Detection in the Massive MIMO

Automatic Modulation Classification for MASK, MPSK, and MQAM Signals Based on Hierarchical Self-Organizing Map

Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router

Efficient MIMO Preprocessor With Sorting-Relaxed QR Decomposition and Modified Greedy LLL Algorithm

Low latency group‐sorted QR decomposition algorithm for larger‐scale MIMO systems

Hardware Architecture Based on Parallel Tiled QRD Algorithm for Future MIMO Systems

High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

A Novel Architecture to Eliminate Bottlenecks in a Parallel Tiled QRD Algorithm for Future MIMO Systems

An Improved Concatenation Scheme of BCH-Polar Codes With Low-Latency Decoding Architecture

An Area-Efficient Hybrid Polar Decoder with Pipelined Architecture

Area-Efficient Parallel Reconfigurable Stream Processor for Symmetric Cryptograph

Deep learning-aided high-precision data detection for massive MU-MIMO systems

A Flexible Divide-and-Conquer MPSoC Architecture for MIMO Interference Cancellation

Approximate iteration detection and precoding in massive MIMO

Algorithm and Architecture for Path Metric Aided Bit-Flipping Decoding of Polar Codes

Architecture and Implementation of a Reduced EPIC Processor

Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

Fei Teng 64 Stream Processing System: Architecture, Compiler, and Programming

Accelerating FDTD simulation of microwave pulse coupling into narrow slots on the Intel MIC architecture

FPGA Implementation for the Sigmoid with Piecewise Linear Fitting Method Based on Curvature Analysis

An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors

Approximate iteration detection with iterative refinement in massive MIMO systems

A model for energy quantization of single-electron transistor below 10nm

Locality based warp scheduling in GPGPUs

Practical AMC model based on SAE with various optimisation methods under different noise environments

Suchergebnisse filtern