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Ascend AI Processor Architecture and Programming

Xiaoyao, Liang

2020

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Ascend AI Processor Architecture and Programming: Principles and Applications of CANN

Liang, Xiaoyao

1, 2020

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Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, p.19-24

2017

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Monolithic 3D integration of 2D transistors and vertical RRAMs in 1T–4R structure for high-density memory

Nature communications, 2023-09, Vol.14 (1), p.5952-5952, Article 5952

2023

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Quantitative analysis of abnormalities in gynecologic cytopathology with deep learning

Laboratory investigation, 2021-04, Vol.101 (4), p.513-524

2021

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Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs

IEEE transactions on computers, 2016-01, Vol.65 (1), p.122-135

2016

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A Learning Algorithm for Bayesian Networks and Its Efficient Implementation on GPUs

IEEE transactions on parallel and distributed systems, 2016-01, Vol.27 (1), p.17-30

2016

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Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency

IEEE MICRO, 2009-01, Vol.29 (1), p.127-138

2009

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A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-07, Vol.35 (7), p.1192-1205

2016

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Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability

IEEE MICRO, 2008-01, Vol.28 (1), p.60-68

2008

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Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU

IEEE transactions on very large scale integration (VLSI) systems, 2017-02, Vol.25 (2), p.520-533

2017

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Sneak-path based test and diagnosis for 1R RRAM crossbar using voltage bias technique

2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 2017, p.1-6

2017

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AXNet: approximate computing using an end-to-end trainable neural network

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018, p.1-8

2018

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Exploring Hardware Profile-Guided Green Datacenter Scheduling

2015 44th International Conference on Parallel Processing, 2015, p.11-20

2015

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Power Attack Defense: Securing Battery-Backed Data Centers

2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), 2016, p.493-505

2016

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Towards sustainable in-situ server systems in the big data era

2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA), 2015, p.14-26

2015

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On quality trade-off control for approximate computing using iterative training

2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 2017, p.1-6

2017

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Compiler assisted dynamic register file in GPGPU

International Symposium on Low Power Electronics and Design (ISLPED), 2013, p.3-8

2013

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Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs

2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2016, p.1-12

2016

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Dynamic front-end sharing in graphics processing units

2014 IEEE 32nd International Conference on Computer Design (ICCD), 2014, p.286-291

2014

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AI Processor Architecture and Programming: Principles and Applications of CANN With Ascend Processor

Liang Xiaoyao (author)

2020

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Defect tolerance for CNFET-based SRAMs

2016 IEEE International Test Conference (ITC), 2016, p.1-9

2016

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CGSharing: Efficient content sharing in GPU-based cloud gaming

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2015, p.171-176

2015

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Fault clustering technique for 3D memory BISR

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, p.560-565

2017

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E 2 -VOR: An End-to-End En/Decoder Architecture for Efficient Video Object Recognition

ACM transactions on design automation of electronic systems, 2023-01, Vol.28 (1), p.1-21

2023

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Ascend AI Processor Architecture and Programming

Ascend AI Processor Architecture and Programming: Principles and Applications of CANN

Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar

Monolithic 3D integration of 2D transistors and vertical RRAMs in 1T–4R structure for high-density memory

Quantitative analysis of abnormalities in gynecologic cytopathology with deep learning

Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs

A Learning Algorithm for Bayesian Networks and Its Efficient Implementation on GPUs

Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency

A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs

Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability

Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU

Sneak-path based test and diagnosis for 1R RRAM crossbar using voltage bias technique

AXNet: approximate computing using an end-to-end trainable neural network

Exploring Hardware Profile-Guided Green Datacenter Scheduling

Power Attack Defense: Securing Battery-Backed Data Centers

Towards sustainable in-situ server systems in the big data era

On quality trade-off control for approximate computing using iterative training

Compiler assisted dynamic register file in GPGPU

Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs

Dynamic front-end sharing in graphics processing units

AI Processor Architecture and Programming: Principles and Applications of CANN With Ascend Processor

Defect tolerance for CNFET-based SRAMs

CGSharing: Efficient content sharing in GPU-based cloud gaming

Fault clustering technique for 3D memory BISR

E 2 -VOR: An End-to-End En/Decoder Architecture for Efficient Video Object Recognition

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