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Growth and Selective Etch of Phosphorus-Doped Silicon/Silicon–Germanium Multilayers Structures for Vertical Transistors Application

Nanoscale research letters, 2020-12, Vol.15 (1), p.225-225, Article 225

2020

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Negative-Capacitance Characteristics in a Steady-State Ferroelectric Capacitor Made of Parallel Domains

IEEE electron device letters, 2017-08, Vol.38 (8), p.1176-1179

2017

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Study of selective isotropic etching Si1−xGex in process of nanowire transistors

Journal of materials science. Materials in electronics, 2020, Vol.31 (1), p.134-143

2020

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Growth of SiGe layers in source and drain regions for 10 nm node complementary metal-oxide semiconductor (CMOS)

Journal of materials science. Materials in electronics, 2020, Vol.31 (1), p.26-33

2020

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Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

IEEE journal of the Electron Devices Society, 2020-01, Vol.8, p.1-1

2020

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A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm

Materials, 2020-02, Vol.13 (3), p.771

2020

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Structure characteristics of electrical treeing in XLPE insulation under high frequencies

Physica. B, Condensed matter, 2011-07, Vol.406 (14), p.2885-2890

2011

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Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors

Nanomaterials (Basel, Switzerland), 2020-04, Vol.10 (4), p.793

2020

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Analysis of electrical tree propagation in XLPE power cable insulation

Physica. B, Condensed matter, 2011-04, Vol.406 (8), p.1556-1560

2011

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Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/High-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium

Nanomaterials (Basel, Switzerland), 2020-08, Vol.10 (9), p.1715

2020

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Investigation of device-circuit for negative capacitance vertical nanowire FETs based on SPICE model

Semiconductor science and technology, 2020-08, Vol.35 (8), p.85018

2020

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First Demonstration of Novel Vertical Gate-All-Around Field-Effect-Transistors Featured by Self-Aligned and Replaced High‑κ Metal Gates

Nano letters, 2021-06, Vol.21 (11), p.4730-4737

2021

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Ferroelectric Vertical Gate-All-Around Field-Effect-Transistors With High Speed, High Density, and Large Memory Window

IEEE electron device letters, 2022-01, Vol.43 (1), p.25-28

2022

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Demonstration of Germanium Vertical Gate-All-Around Field-Effect Transistors Featured by Self-Aligned High-κ Metal Gates with Record High Performance

ACS nano, 2023-11, Vol.17 (22), p.22259-22267

2023

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Vertical Sandwich Gate-All-Around Field-Effect Transistors With Self-Aligned High-k Metal Gates and Small Effective-Gate-Length Variation

IEEE electron device letters, 2020-01, Vol.41 (1), p.8-11

2020

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Investigation of ferroelectric field-effect transistors using a replacement metal gate process

Semiconductor science and technology, 2021-03, Vol.36 (3), p.35003

2021

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Vertical Sandwich GAA FETs With Self-Aligned High-k Metal Gate Made by Quasi Atomic Layer Etching Process

IEEE transactions on electron devices, 2021-06, Vol.68 (6), p.2604-2610

2021

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Selective Digital Etching of Silicon–Germanium Using Nitric and Hydrofluoric Acids

ACS applied materials & interfaces, 2020-10, Vol.12 (42), p.48170-48178

2020

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Comparative study on NBTI kinetics in Si p-FinFETs with B2H6-based and SiH4-based atomic layer deposition tungsten (ALD W) filling metal

Microelectronics and reliability, 2020-04, Vol.107, p.113627, Article 113627

2020

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Harmonic measurements and analysis in a modern steel manufacturing facility

IEEE PES General Meeting, 2010, p.1-6

2010

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Simulations of VNW-FETs with Adjustable Spacer-Like Negative Capacitors Based on Experimental Data

ECS journal of solid state science and technology, 2019-01, Vol.8 (2), p.Q38-Q42

2019

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Influence of Dopants Profile on Random Dopant Fluctuation and Optimization for Bulk FinFET

ECS journal of solid state science and technology, 2017, Vol.6 (7), p.M79-M82

2017

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Study of Isotropic and Si-Selective Quasi Atomic Layer Etching of Si 1−x Ge x

ECS journal of solid state science and technology, 2020-03, Vol.9 (3), p.34012

2020

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Investigation of negative DIBL effect for ferroelectric-based FETs to improve MOSFETs and CMOS circuits

Microelectronics, 2021-08, Vol.114, p.105110, Article 105110

2021

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Advanced TEM Application in 10nm below Technology Node Device Analysis

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), 2019, p.1-4

2019

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Growth and Selective Etch of Phosphorus-Doped Silicon/Silicon–Germanium Multilayers Structures for Vertical Transistors Application

Negative-Capacitance Characteristics in a Steady-State Ferroelectric Capacitor Made of Parallel Domains

Study of selective isotropic etching Si1−xGex in process of nanowire transistors

Growth of SiGe layers in source and drain regions for 10 nm node complementary metal-oxide semiconductor (CMOS)

Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm

Structure characteristics of electrical treeing in XLPE insulation under high frequencies

Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors

Analysis of electrical tree propagation in XLPE power cable insulation

Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/High-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium

Investigation of device-circuit for negative capacitance vertical nanowire FETs based on SPICE model

First Demonstration of Novel Vertical Gate-All-Around Field-Effect-Transistors Featured by Self-Aligned and Replaced High‑κ Metal Gates

Ferroelectric Vertical Gate-All-Around Field-Effect-Transistors With High Speed, High Density, and Large Memory Window

Demonstration of Germanium Vertical Gate-All-Around Field-Effect Transistors Featured by Self-Aligned High-κ Metal Gates with Record High Performance

Vertical Sandwich Gate-All-Around Field-Effect Transistors With Self-Aligned High-k Metal Gates and Small Effective-Gate-Length Variation

Investigation of ferroelectric field-effect transistors using a replacement metal gate process

Vertical Sandwich GAA FETs With Self-Aligned High-k Metal Gate Made by Quasi Atomic Layer Etching Process

Selective Digital Etching of Silicon–Germanium Using Nitric and Hydrofluoric Acids

Comparative study on NBTI kinetics in Si p-FinFETs with B2H6-based and SiH4-based atomic layer deposition tungsten (ALD W) filling metal

Harmonic measurements and analysis in a modern steel manufacturing facility

Simulations of VNW-FETs with Adjustable Spacer-Like Negative Capacitors Based on Experimental Data

Influence of Dopants Profile on Random Dopant Fluctuation and Optimization for Bulk FinFET

Study of Isotropic and Si-Selective Quasi Atomic Layer Etching of Si 1−x Ge x

Investigation of negative DIBL effect for ferroelectric-based FETs to improve MOSFETs and CMOS circuits

Advanced TEM Application in 10nm below Technology Node Device Analysis

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