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Modeling the Distributive Effects of RC Transmission Line Using Recursive Segmentation and Applications to MOSFETs and BJTs

IEEE transactions on electron devices, 2016-09, Vol.63 (9), p.3385-3392

Xia, Kejun

2016

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Well-Conditioned MOSFET Surface Potential Equation for Cryogenic Temperatures and Its Analytical Approximation

IEEE transactions on electron devices, 2023-11, Vol.70 (11), p.5557-5562

Xia, Kejun

2023

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Trinity Theology and the Gift Economy of Forming a Spiritual Authority

Contemporary Chinese thought, 2016-10, Vol.47 (4), p.270-285

Kejun, Xia

2016

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A Simple Method to Create Corners for the Lookup Table-Based MOSFET Models Through Inputs and Outputs Mapping

IEEE transactions on electron devices, 2021-04, Vol.68 (4), p.1432-1438

Xia, Kejun

2021

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New C∞ Functions for Drain-Source Voltage Clamping in Transistor Modeling

IEEE transactions on electron devices, 2020-04, Vol.67 (4), p.1-5

Xia, Kejun

2020

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Symmetric Source and Drain Voltage Clamping Scheme for Complete Source-Drain Symmetry in Field-Effect Transistor Modeling

IEEE transactions on electron devices, 2020-08, Vol.67 (8), p.3042-3048

Xia, Kejun

2020

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Dual-Gate JFET Modeling I: Generalization to Include MOS Gates and Efficient Method to Calculate Drain-Source Saturation Voltage

IEEE transactions on electron devices, 2016-04, Vol.63 (4), p.1408-1415

2016

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Effect of Boundary Conditions on Thermal Noise of Intrinsic Terminal Currents in Bipolar Transistors Pertinent to Quasi-Ballistic Transport

IEEE transactions on electron devices, 2013-12, Vol.60 (12), p.4226-4233

2013

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Dual-Gate JFET Modeling II: Source Pinchoff Voltage and Complete Modeling Formalism

IEEE transactions on electron devices, 2016-04, Vol.63 (4), p.1416-1422

2016

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A New Approach to Implementing High-Frequency Correlated Noise for Bipolar Transistor Compact Modeling

IEEE transactions on electron devices, 2012-02, Vol.59 (2), p.302-308

2012

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Parameter Extraction for the PSPHV LDMOS Transistor Model

IEEE journal of the Electron Devices Society, 2020, Vol.8, p.813-824

2020

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Smoothing globally continuous piecewise functions based on limiting functions for device compact modeling

Journal of computational electronics, 2019-09, Vol.18 (3), p.1025-1036

Xia, Kejun

2019

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Modeling the input non-quasi-static effect in small signal equivalent circuit based on charge partitioning for bipolar transistors and its impact on RF noise modeling

Solid-state electronics, 2010-12, Vol.54 (12), p.1566-1571

2010

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Foreword Special Issue on Compact Modeling of Semiconductor Devices

IEEE journal of the Electron Devices Society, 2020, Vol.8, p.1350-1353

2020

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Dialectics of blandness: the contemporaneity of Su Shi's aesthetics

Journal of visual art practice, 2023-10, Vol.22 (4), p.331-345

2023

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Discussions and extension of van Vliet’s noise model for high speed bipolar transistors

Solid-state electronics, 2009-03, Vol.53 (3), p.349-354

2009

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JFETIDG: A Compact Model for Independent Dual-Gate JFETs With Junction or MOS Gates

IEEE transactions on electron devices, 2018-02, Vol.65 (2), p.747-755

2018

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Frequency and bias-dependent modeling of correlated base and collector current RF noise in SiGe HBTs using quasi-static equivalent circuit

IEEE transactions on electron devices, 2006-03, Vol.53 (3), p.515-522

2006

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Compact modeling of LDMOS working in the third quadrant

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014, p.1-4

2014

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Impedance and Effective Resistance of Capacitors With Resistive Top and Bottom Plates

IEEE transactions on electron devices, 2021-10, Vol.68 (10), p.4834-4841

2021

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Dual-Gate JFET Modeling II: Source Pinchoff Voltage and Complete I} Modeling Formalism

IEEE transactions on electron devices, 2016-04, Vol.63 (4), p.1416-1422

2016

Volltextzugriff (PDF)

A Step-by-Step Layout Transformation Approach to Differentiate How Multiple Layout Dependent Effects Modify Device and Circuit Performance

2024 IEEE 36th International Conference on Microelectronic Test Structures (ICMTS), 2024, p.1-5

2024

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PSPHV: A Surface-Potential-Based Model for LDMOS Transistors

IEEE transactions on electron devices, 2019-12, Vol.66 (12), p.5246-5253

2019

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Accurate Gate Charge Modeling of HV LDMOS Transistors for Power Circuit Applications

2023 35th International Conference on Microelectronic Test Structure (ICMTS), 2023, p.1-5

2023

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Impact of Collector-Base Space Charge Region on RF Noise in Bipolar Transistors

2006 Bipolar/BiCMOS Circuits and Technology Meeting, 2006, p.1-4

2006

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Modeling the Distributive Effects of RC Transmission Line Using Recursive Segmentation and Applications to MOSFETs and BJTs

Well-Conditioned MOSFET Surface Potential Equation for Cryogenic Temperatures and Its Analytical Approximation

Trinity Theology and the Gift Economy of Forming a Spiritual Authority

A Simple Method to Create Corners for the Lookup Table-Based MOSFET Models Through Inputs and Outputs Mapping

New C∞ Functions for Drain-Source Voltage Clamping in Transistor Modeling

Symmetric Source and Drain Voltage Clamping Scheme for Complete Source-Drain Symmetry in Field-Effect Transistor Modeling

Dual-Gate JFET Modeling I: Generalization to Include MOS Gates and Efficient Method to Calculate Drain-Source Saturation Voltage

Effect of Boundary Conditions on Thermal Noise of Intrinsic Terminal Currents in Bipolar Transistors Pertinent to Quasi-Ballistic Transport

Dual-Gate JFET Modeling II: Source Pinchoff Voltage and Complete Modeling Formalism

A New Approach to Implementing High-Frequency Correlated Noise for Bipolar Transistor Compact Modeling

Parameter Extraction for the PSPHV LDMOS Transistor Model

Smoothing globally continuous piecewise functions based on limiting functions for device compact modeling

Modeling the input non-quasi-static effect in small signal equivalent circuit based on charge partitioning for bipolar transistors and its impact on RF noise modeling

Foreword Special Issue on Compact Modeling of Semiconductor Devices

Dialectics of blandness: the contemporaneity of Su Shi's aesthetics

Discussions and extension of van Vliet’s noise model for high speed bipolar transistors

JFETIDG: A Compact Model for Independent Dual-Gate JFETs With Junction or MOS Gates

Frequency and bias-dependent modeling of correlated base and collector current RF noise in SiGe HBTs using quasi-static equivalent circuit

Compact modeling of LDMOS working in the third quadrant

Impedance and Effective Resistance of Capacitors With Resistive Top and Bottom Plates

Dual-Gate JFET Modeling II: Source Pinchoff Voltage and Complete I} Modeling Formalism

A Step-by-Step Layout Transformation Approach to Differentiate How Multiple Layout Dependent Effects Modify Device and Circuit Performance

PSPHV: A Surface-Potential-Based Model for LDMOS Transistors

Accurate Gate Charge Modeling of HV LDMOS Transistors for Power Circuit Applications

Impact of Collector-Base Space Charge Region on RF Noise in Bipolar Transistors

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