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The N3XT Approach to Energy-Efficient Abundant-Data Computing

Proceedings of the IEEE, 2019-01, Vol.107 (1), p.19-48

2019

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Energy-Efficient Abundant-Data Computing: The N3XT 1,000x

Computer (Long Beach, Calif.), 2015-12, Vol.48 (12), p.24-33

2015

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TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-04, Vol.35 (4), p.521-534

2016

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Carbon Nanotube Circuit Integration up to Sub-20 nm Channel Lengths

ACS nano, 2014-04, Vol.8 (4), p.3434-3443

2014

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Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration

IEEE journal of solid-state circuits, 2018-11, Vol.53 (11), p.3183-3196

2018

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Resistive RAM-Centric Computing: Design and Modeling Methodology

IEEE transactions on circuits and systems. I, Regular papers, 2017-09, Vol.64 (9), p.2263-2273

2017

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RADAR: A Fast and Energy-Efficient Programming Technique for Multiple Bits-Per-Cell RRAM Arrays

IEEE transactions on electron devices, 2021-09, Vol.68 (9), p.4397-4403

2021

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A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries

2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2023, p.58-59

2023

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System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars

2022 IEEE Custom Integrated Circuits Conference (CICC), 2022, p.01-08

2022

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Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.216-217

2022

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Efficient metallic carbon nanotube removal for highly-scaled technologies

2015 IEEE International Electron Devices Meeting (IEDM), 2015, p.32.4.1-32.4.4

2015

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Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.492-494

2018

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Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs

2014 IEEE International Electron Devices Meeting, 2014, p.27.4.1-27.4.4

2014

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Illusion of large on-chip memory by networked computing chips for neural network inference

Nature electronics, 2021-01, Vol.4 (1), p.71-80

2021

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Monolithic 3D integration: A path from concept to reality

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, p.1197-1202

2015

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11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.210-212

2024

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14.3 A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.226-228

2019

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Monolithic 3D integration: a path from concept to reality

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015, p.1197-1202

2015

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Monolithic 3D integration advances and challenges: From technology to system levels

2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014, p.1-2

2014

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Evaluation of Low-Voltage SRAM for Error-Resilient Augmented Reality Applications

2021 IEEE Workshop on Signal Processing Systems (SiPS), 2021, p.1-3

2021

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Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition

2016 IEEE International Electron Devices Meeting (IEDM), 2016, p.16.1.1-16.1.4

2016

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Device-architecture co-design for hyperdimensional computing with 3d vertical resistive switching random access memory (3D VRRAM)

2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2017, p.1-2

2017

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Cooling three-dimensional integrated circuits using power delivery networks

2012 International Electron Devices Meeting, 2012, p.14.2.1-14.2.4

2012

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3D nanosystems enable embedded abundant-data computing: special session paper

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017, p.1-2

2017

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Special session paper 3D nanosystems enable embedded abundant-data computing

2017 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2017, p.1-2

2017

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The N3XT Approach to Energy-Efficient Abundant-Data Computing

Energy-Efficient Abundant-Data Computing: The N3XT 1,000x

TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits

Carbon Nanotube Circuit Integration up to Sub-20 nm Channel Lengths

Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration

Resistive RAM-Centric Computing: Design and Modeling Methodology

RADAR: A Fast and Energy-Efficient Programming Technique for Multiple Bits-Per-Cell RRAM Arrays

A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries

System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars

Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications

Efficient metallic carbon nanotube removal for highly-scaled technologies

Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study

Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs

Illusion of large on-chip memory by networked computing chips for neural network inference

Monolithic 3D integration: A path from concept to reality

11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint

14.3 A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques

Monolithic 3D integration: a path from concept to reality

Monolithic 3D integration advances and challenges: From technology to system levels

Evaluation of Low-Voltage SRAM for Error-Resilient Augmented Reality Applications

Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition

Device-architecture co-design for hyperdimensional computing with 3d vertical resistive switching random access memory (3D VRRAM)

Cooling three-dimensional integrated circuits using power delivery networks

3D nanosystems enable embedded abundant-data computing: special session paper

Special session paper 3D nanosystems enable embedded abundant-data computing

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