UB Paderborn / Katalog / Suche / in CDI

Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-03, Vol.26 (3), p.564-573

2007

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A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements

IEEE transactions on very large scale integration (VLSI) systems, 2017-03, Vol.25 (3), p.820-832

2017

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A novel privacy-preserving deep learning scheme without a cryptography component

Computers & electrical engineering, 2021-09, Vol.94, p.107325, Article 107325

2021

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A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, p.79-84

2016

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Scheduling techniques for variable voltage low power designs

ACM transactions on design automation of electronic systems, 1997-04, Vol.2 (2), p.81-97

1997

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A predictive system shutdown method for energy saving of event-driven computation

ACM transactions on design automation of electronic systems, 2000-04, Vol.5 (2), p.226-241

2000

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A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration

ACM transactions on design automation of electronic systems, 2024-07, Vol.29 (4), p.1-27, Article 70

2024

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A Dynamic Link-latency Aware Cache Replacement Policy (DLRP)

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC), 2021, p.210-215

2021

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Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs

2019 32nd IEEE International System-on-Chip Conference (SOCC), 2019, p.236-241

2019

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Crosstalk-aware TSV-buffer Insertion in 3D IC

2019 32nd IEEE International System-on-Chip Conference (SOCC), 2019, p.400-405

2019

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Datapath Optimization Using Layout Information: An Empirical Study

VLSI Design, 1997-01, Vol.1997 (2), p.195-209

Wu, Allen C.-H.

1997

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Multiway FPGA partitioning by fully exploiting design hierarchy

ACM transactions on design automation of electronic systems, 2000-01, Vol.5 (1), p.34-50

2000

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A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs

Design, Automation, and Test in Europe: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1; 03-07 Mar. 2003, 2003, p.11102-11102

2003

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The Design and Implementation of a Cooperative Design-view Environment for Interactive Partitioning Applications

Software, practice & experience, 1996-10, Vol.26 (10), p.1141-1160

1996

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G-MAC: An Application-Specific MAC/Co-Processor Synthesizer

Design, Automation, and Test in Europe: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1; 03-07 Mar. 2003, 2003, p.11134-11134

2003

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A timing-driven soft-macro resynthesis method in interaction with chip floorplanning

Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 1999, p.262-267

1999

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Module generation of high performance FPGA-based multipliers

International Symposium on Field Programmable Gate Arrays: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays; 21-23 Feb. 1999, 1999, p.251-251

1999

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Performance-driven multi-FPGA partitioning using functional clustering and replication

Annual ACM IEEE Design Automation Conference: Proceedings of the 35th annual conference on Design automation; 15-19 June 1998, 1998, p.283-286

1998

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A power-driven multiplication instruction-set design method for ASIPs

IEEE transactions on very large scale integration (VLSI) systems, 2006-01, Vol.14 (1), p.81-85

2006

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An RTL design-space exploration method for high-level applications

Proceedings of the 2001 Asia and South Pacific Design Automation Conference, 2001, p.162-168

2001

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A real-time RTL engineering-change method supporting on-line debugging for logic-emulation applications

Annual ACM IEEE Design Automation Conference: Proceedings of the 34th annual conference on Design automation; 09-13 June 1997, 1997, p.101-106

1997

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Multi-way FPGA partitioning by fully exploiting design hierarchy

Annual ACM IEEE Design Automation Conference: Proceedings of the 34th annual conference on Design automation; 09-13 June 1997, 1997, p.518-521

1997

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EmGen-a module generator for logic emulation applications

IEEE transactions on very large scale integration (VLSI) systems, 1999-12, Vol.7 (4), p.488-492

1999

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EMPAR: an interactive synthesis environment for hardware emulations

Proceedings of the 1995 Asia and South Pacific Design Automation Conference, 1995, p.15-15-es

1995

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A performance and routablity driven router for FPGAs considering path delays

Annual ACM IEEE Design Automation Conference: Proceedings of the 32nd ACM/IEEE conference on Design automation; 12-16 June 1995, 1995, p.557-561

1995

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Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment

A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements

A novel privacy-preserving deep learning scheme without a cryptography component

A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements

Scheduling techniques for variable voltage low power designs

A predictive system shutdown method for energy saving of event-driven computation

A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration

A Dynamic Link-latency Aware Cache Replacement Policy (DLRP)

Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs

Crosstalk-aware TSV-buffer Insertion in 3D IC

Datapath Optimization Using Layout Information: An Empirical Study

Multiway FPGA partitioning by fully exploiting design hierarchy

A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs

The Design and Implementation of a Cooperative Design-view Environment for Interactive Partitioning Applications

G-MAC: An Application-Specific MAC/Co-Processor Synthesizer

A timing-driven soft-macro resynthesis method in interaction with chip floorplanning

Module generation of high performance FPGA-based multipliers

Performance-driven multi-FPGA partitioning using functional clustering and replication

A power-driven multiplication instruction-set design method for ASIPs

An RTL design-space exploration method for high-level applications

A real-time RTL engineering-change method supporting on-line debugging for logic-emulation applications

Multi-way FPGA partitioning by fully exploiting design hierarchy

EmGen-a module generator for logic emulation applications

EMPAR: an interactive synthesis environment for hardware emulations

A performance and routablity driven router for FPGAs considering path delays

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