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A Novel Multifin Dynamic Random Access Memory Periphery Transistor Technology Using a Spacer Patterning through Gate Polycrystalline Silicon Technique
Japanese Journal of Applied Physics, 2009-04, Vol.48 (4S), p.4
2009
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A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies
2013 IEEE International Electron Devices Meeting, 2013, p.26.5.1-26.5.4
2013
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Electrical Failure Analysis Methodology for DRAM of 80nm era and beyond using Nanoprober Technique
2007 IEEE International Conference on Microelectronic Test Structures, 2007, p.55-58
2007
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Drain leakage fluctuation reduction in the recessed channel array transistor DRAM with the elevated source-drain
2006 European Solid-State Device Research Conference, 2006, p.254-257
2006
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Shallow Trench Isolation Characteristics with High-Density-Plasma Chemical Vapor Deposition Gap-Fill Oxide for Deep-Submicron CMOS Technologies
Japanese Journal of Applied Physics, 1998-03, Vol.37 (3S), p.1222
1998
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A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n+-doped polysilicon
IEEE transactions on electron devices, 2004-10, Vol.51 (10), p.1644-1652
2004
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A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n/sup +/-doped polysilicon
IEEE transactions on electron devices, 2004-10, Vol.51 (10), p.1644-1652
2004
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A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n super(+)-doped polysilicon
IEEE transactions on electron devices, 2004-01, Vol.51 (10)
2004
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Three Series-Connected Transistor Model for a Recess-Channel-Array Transistor and Improvement of Electrical Characteristics by a Bottom Fin Structure
Japanese Journal of Applied Physics, 2009-05, Vol.48 (5R), p.54504
2009
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Recessed Channel Fin Field-Effect Transistor Cell Technology for Future-Generation Dynamic Random Access Memories
Japanese Journal of Applied Physics, 2008-04, Vol.47 (4S), p.2672
2008
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Investigation of Body Bias Dependence of Gate-Induced Drain Leakage Current for Body-Tied Fin Field Effect Transistor
Japanese Journal of Applied Physics, 2008-09, Vol.47 (9R), p.7065
2008
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Fully Integrated Advanced Bulk FinFETs Architecture Featuring Partially-Insulating Technique for DRAM Cell Application of 40nm Generation and Beyond
2006 International Electron Devices Meeting, 2006, p.1-4
2006
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A Novel Body Effect Reduction Technique to Recessed Channel Transistor Featuring Partially Insulating Layer Under Source and Drain : Application to Sub-50nm DRAM Cell
2007 IEEE International Electron Devices Meeting, 2007, p.903-906
2007
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Reliability Investigations for Bulk-FinFETs Implementing Partially-Insulating Layer
2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, 2007, p.378-381
2007
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A Full FinFET DRAM Core Integration Technology Using a Simple Selective Fin Formation Technique
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers, 2006, p.34-35
2006
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New anti-punchthrough design for buried channel PMOSFET
27th European Solid-State Device Research Conference, 1997, p.232-235
1997
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A new process integration-P/sup 3/ (pre poly plug)-for giga bit DRAM era
1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325), 1999, p.37-38
1999
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Comparative study of several anti-punchthrough designs for buried channel PMOSFET
1997 55th Annual Device Research Conference Digest, 1997, p.18-19
1997
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