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Wafer-level 3D integration technology

IBM journal of research and development, 2008-11, Vol.52 (6), p.583-597

2008

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Fault-tolerant designs for 256 Mb DRAM

IEEE journal of solid-state circuits, 1996-04, Vol.31 (4), p.558-566

1996

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A new 'shift and ratio' method for MOSFET channel-length extraction

IEEE electron device letters, 1992-05, Vol.13 (5), p.267-269

1992

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Generalized scaling theory and its application to a 1/4 micrometer MOSFET design

IEEE transactions on electron devices, 1984-01, Vol.ED-31 (4), p.452-461

1984

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High transconductance and velocity overshoot in NMOS devices at the 0.1- mu m gate-length level

IEEE electron device letters, 1988-09, Vol.9 (9), p.464-466

1988

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1-GHz fully pipelined 3.7-ns address access time 8 k x 1024 embedded synchronous DRAM macro

IEEE journal of solid-state circuits, 2000-11, Vol.35 (11), p.1673-1679

2000

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A high-performance 0.25- mu m CMOS technology. I. Design and characterization

IEEE transactions on electron devices, 1992-04, Vol.39 (4), p.959-966

1992

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1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro

IEEE journal of solid-state circuits, 2000-11, Vol.35 (11), p.1673

2000

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A high-performance 0.25- mu m CMOS technology. II. Technology

IEEE transactions on electron devices, 1992-04, Vol.39 (4), p.967-975

1992

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Flexible test mode approach for 256-Mb DRAM

IEEE journal of solid-state circuits, 1997-10, Vol.32 (10), p.1525-1534

1997

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A 7F(2) cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

IEEE journal of solid-state circuits, 2000-05, Vol.35 (5), p.713-718

2000

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Transconductance degradation in thin-Oxide MOSFET's

IEEE transactions on electron devices, 1983-10, Vol.30 (10), p.1295-1304

1983

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Design and experimental technology for 0.1-μm gate-length low-temperature operation FET's

IEEE electron device letters, 1987, Vol.8 (10), p.463-466

1987

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220-mm super(2), four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture

IEEE journal of solid-state circuits, 1998-11, Vol.33 (11), p.1711-1718

1998

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A shorted global clock design for multi-GHz 3D stacked chips

2012 Symposium on VLSI Circuits (VLSIC), 2012, p.170-171

2012

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A comprehensive study of hot-carrier instability in p- and n-type poly-Si gated MOSFET's

IEEE transactions on electron devices, 1994-05, Vol.41 (5), p.675-680

1994

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On the accuracy of channel length characterization of LDD MOSFET's

IEEE transactions on electron devices, 1986-10, Vol.33 (10), p.1556-1562

1986

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Alpha-particle-induced soft error rate in VLSI circuits

IEEE transactions on electron devices, 1982-04, Vol.29 (4), p.725-731

1982

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286 mm super(2) 256 Mb DRAM with x 32 both-ends DQ

IEEE journal of solid-state circuits, 1996-01, Vol.31 (4), p.567-574

1996

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Inverter performance of deep-submicrometer MOSFETs

IEEE electron device letters, 1988-12, Vol.9 (12), p.633-635

1988

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IIIB-1 degradation of 77-K MOSFET characteristics due to channel hot electrons

IEEE transactions on electron devices, 1984-12, Vol.31 (12), p.1970-1970

1984

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MOSFET miniaturization — From one micron to the limits

Physica B + C, 1985-01, Vol.129 (1), p.3-15

1985

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Threshold voltage characteristics of depletion-mode MOSFET's

IEEE transactions on electron devices, 1981-09, Vol.28 (9), p.1025-1030

1981

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Alpha-Particle-Induced Soft Error Rate in VLSI Circuits

IEEE journal of solid-state circuits, 1982-04, Vol.17 (2), p.355-361

1982

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A fully scaled submicrometer NMOS technology using direct-write E-beam lithography

IEEE transactions on electron devices, 1985-01, Vol.32 (11), p.2214-2223

1985

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Wafer-level 3D integration technology

Fault-tolerant designs for 256 Mb DRAM

A new 'shift and ratio' method for MOSFET channel-length extraction

Generalized scaling theory and its application to a 1/4 micrometer MOSFET design

High transconductance and velocity overshoot in NMOS devices at the 0.1- mu m gate-length level

1-GHz fully pipelined 3.7-ns address access time 8 k x 1024 embedded synchronous DRAM macro

A high-performance 0.25- mu m CMOS technology. I. Design and characterization

1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro

A high-performance 0.25- mu m CMOS technology. II. Technology

Flexible test mode approach for 256-Mb DRAM

A 7F(2) cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

Transconductance degradation in thin-Oxide MOSFET's

Design and experimental technology for 0.1-μm gate-length low-temperature operation FET's

220-mm super(2), four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture

A shorted global clock design for multi-GHz 3D stacked chips

A comprehensive study of hot-carrier instability in p- and n-type poly-Si gated MOSFET's

On the accuracy of channel length characterization of LDD MOSFET's

Alpha-particle-induced soft error rate in VLSI circuits

286 mm super(2) 256 Mb DRAM with x 32 both-ends DQ

Inverter performance of deep-submicrometer MOSFETs

IIIB-1 degradation of 77-K MOSFET characteristics due to channel hot electrons

MOSFET miniaturization — From one micron to the limits

Threshold voltage characteristics of depletion-mode MOSFET's

Alpha-Particle-Induced Soft Error Rate in VLSI Circuits

A fully scaled submicrometer NMOS technology using direct-write E-beam lithography

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