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A new 'shift and ratio' method for MOSFET channel-length extraction

IEEE electron device letters, 1992-05, Vol.13 (5), p.267-269

1992

Volltextzugriff (PDF)

An investigation of steady-state velocity overshoot in silicon

Solid-state electronics, 1985-01, Vol.28 (4), p.407-416

1985

Volltextzugriff (PDF)

High transconductance and velocity overshoot in NMOS devices at the 0.1- mu m gate-length level

IEEE electron device letters, 1988-09, Vol.9 (9), p.464-466

1988

Volltextzugriff (PDF)

A high-performance 0.25- mu m CMOS technology. I. Design and characterization

IEEE transactions on electron devices, 1992-04, Vol.39 (4), p.959-966

1992

Volltextzugriff (PDF)

A high-performance 0.25- mu m CMOS technology. II. Technology

IEEE transactions on electron devices, 1992-04, Vol.39 (4), p.967-975

1992

Volltextzugriff (PDF)

Process-design considerations for three dimensional memory integration

2009 Symposium on VLSI Technology, 2009, p.60-63

2009

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On the accuracy of channel length characterization of LDD MOSFET's

IEEE transactions on electron devices, 1986-10, Vol.33 (10), p.1556-1562

1986

Volltextzugriff (PDF)

Hot-electron-induced instability in 0.5- mu m p-channel MOSFETs patterned using synchrotron X-ray lithography

IEEE electron device letters, 1989-07, Vol.10 (7), p.327-329

1989

Volltextzugriff (PDF)

Geometry effects in MOSFET channel length extraction algorithms

IEEE electron device letters, 1985-04, Vol.6 (4), p.186-188

1985

Volltextzugriff (PDF)

Generalized scaling theory and its application to a ¼ micrometer MOSFET design

IEEE transactions on electron devices, 1984-04, Vol.31 (4), p.452-462

1984

Volltextzugriff (PDF)

1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro

IEEE journal of solid-state circuits, 2000-11, Vol.35 (11), p.1673

2000

Volltextzugriff (PDF)

Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's

IEEE electron device letters, 1987-10, Vol.8 (10), p.463-466

1987

Volltextzugriff (PDF)

Fault-tolerant designs for 256 Mb DRAM

IEEE journal of solid-state circuits, 1996-04, Vol.31 (4), p.558-566

1996

Volltextzugriff (PDF)

1-GHz fully pipelined 3.7-ns address access time 8 k/spl times/1024 embedded synchronous DRAM macro

IEEE journal of solid-state circuits, 2000-11, Vol.35 (11), p.1673-1679

2000

Volltextzugriff (PDF)

Flexible test mode approach for 256-Mb DRAM

IEEE journal of solid-state circuits, 1997-10, Vol.32 (10), p.1525-1534

1997

Volltextzugriff (PDF)

A 390-mm/sup 2/, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture

IEEE journal of solid-state circuits, 1999-11, Vol.34 (11), p.1580-1588

1999

Volltextzugriff (PDF)

Transconductance degradation in thin-Oxide MOSFET's

IEEE transactions on electron devices, 1983-10, Vol.30 (10), p.1295-1304

1983

Volltextzugriff (PDF)

A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

IEEE journal of solid-state circuits, 2000-05, Vol.35 (5), p.713

2000

Volltextzugriff (PDF)

A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

IEEE journal of solid-state circuits, 2000-05, Vol.35 (5), p.713-718

2000

Volltextzugriff (PDF)

A 220-mm/sup 2/, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture

IEEE journal of solid-state circuits, 1998-11, Vol.33 (11), p.1711-1719

1998

Volltextzugriff (PDF)

A comprehensive study of hot-carrier instability in p- and n-type poly-Si gated MOSFET's

IEEE transactions on electron devices, 1994-05, Vol.41 (5), p.675-680

1994

Volltextzugriff (PDF)

A 286 mm/sup 2/ 256 Mb DRAM with /spl times/32 both-ends DQ

IEEE journal of solid-state circuits, 1996-04, Vol.31 (4), p.567-574

1996

Volltextzugriff (PDF)

A 286 mm/sup 2/ 256 Mb DRAM with ×32 both-ends DQ

IEEE journal of solid-state circuits, 1996-04, Vol.31 (4), p.567-574

1996

Volltextzugriff (PDF)

Alpha-particle-induced soft error rate in VLSI circuits

IEEE transactions on electron devices, 1982-04, Vol.29 (4), p.725-731

1982

Volltextzugriff (PDF)

Inverter performance of deep-submicrometer MOSFETs

IEEE electron device letters, 1988-12, Vol.9 (12), p.633-635

1988

Volltextzugriff (PDF)

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A new 'shift and ratio' method for MOSFET channel-length extraction

An investigation of steady-state velocity overshoot in silicon

High transconductance and velocity overshoot in NMOS devices at the 0.1- mu m gate-length level

A high-performance 0.25- mu m CMOS technology. I. Design and characterization

A high-performance 0.25- mu m CMOS technology. II. Technology

Process-design considerations for three dimensional memory integration

On the accuracy of channel length characterization of LDD MOSFET's

Hot-electron-induced instability in 0.5- mu m p-channel MOSFETs patterned using synchrotron X-ray lithography

Geometry effects in MOSFET channel length extraction algorithms

Generalized scaling theory and its application to a ¼ micrometer MOSFET design

1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro

Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's

Fault-tolerant designs for 256 Mb DRAM

1-GHz fully pipelined 3.7-ns address access time 8 k/spl times/1024 embedded synchronous DRAM macro

Flexible test mode approach for 256-Mb DRAM

A 390-mm/sup 2/, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture

Transconductance degradation in thin-Oxide MOSFET's

A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

A 220-mm/sup 2/, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture

A comprehensive study of hot-carrier instability in p- and n-type poly-Si gated MOSFET's

A 286 mm/sup 2/ 256 Mb DRAM with /spl times/32 both-ends DQ

A 286 mm/sup 2/ 256 Mb DRAM with ×32 both-ends DQ

Alpha-particle-induced soft error rate in VLSI circuits

Inverter performance of deep-submicrometer MOSFETs

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