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Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes

IEEE transactions on nanotechnology, 2009-07, Vol.8 (4), p.498-504

2009

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IEEE_Xplore

Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits

IEEE transactions on nanotechnology, 2009-01, Vol.8 (1), p.37-45

2009

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IEEE_Xplore

Impact of a Process Variation on Nanowire and Nanotube Device Performance

IEEE transactions on electron devices, 2007-09, Vol.54 (9), p.2369-2376

2007

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IEEE_Xplore

Electrical characterization of germanium p-channel MOSFETs

IEEE electron device letters, 2003-04, Vol.24 (4), p.242-244

2003

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IEEE_Xplore

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application-Part I: Model of the Intrinsic Channel Region

IEEE transactions on electron devices, 2007-12, Vol.54 (12), p.3186-3194

2007

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IEEE_Xplore

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application-Part II: Full Device Model and Circuit Performance Benchmarking

IEEE transactions on electron devices, 2007-12, Vol.54 (12), p.3195-3205

2007

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IEEE_Xplore

Ultralow Voltage Crossbar Nonvolatile Memory Based on Energy-Reversible NEM Switches

IEEE electron device letters, 2009-06, Vol.30 (6), p.626-628

2009

Link zum Volltext
IEEE_Xplore

Extension and source/drain design for high-performance FinFET devices

IEEE transactions on electron devices, 2003-04, Vol.50 (4), p.952-958

2003

Link zum Volltext
IEEE_Xplore

Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate

IEEE electron device letters, 2004-03, Vol.25 (3), p.135-137

2004

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IEEE_Xplore

Technology projections of III–V devices down to 11 nm: importance of electrostatics and series resistance

Electronics letters, 2013-06, Vol.49 (13), p.832-833

2013

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Analysis of Temperature in Phase Change Memory Scaling

IEEE electron device letters, 2007-08, Vol.28 (8), p.697-699

2007

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IEEE_Xplore

Metrics for performance benchmarking of nanoscale Si and carbon nanotube FETs including device nonidealities

IEEE transactions on electron devices, 2006-06, Vol.53 (6), p.1317-1322

2006

Link zum Volltext
IEEE_Xplore

Modeling and Analysis of Planar-Gate Electrostatic Capacitance of 1-D FET With Multiple Cylindrical Conducting Channels

IEEE transactions on electron devices, 2007-09, Vol.54 (9), p.2377-2385

2007

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IEEE_Xplore

Thermal Boundary Resistance Measurements for Phase-Change Memory Devices

IEEE electron device letters, 2010-01, Vol.31 (1), p.56-58

2010

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IEEE_Xplore

Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-10, Vol.27 (10), p.1725-1736

2008

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IEEE_Xplore

Strained Si CMOS (SS CMOS) technology: opportunities and challenges

Solid-state electronics, 2003-07, Vol.47 (7), p.1133-1139

2003

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Verfügbarkeit prüfen

Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power Logic

IEEE transactions on electron devices, 2008-01, Vol.55 (1), p.48-59

2008

Link zum Volltext
IEEE_Xplore

ACCNT-A Metallic-CNT-Tolerant Design Methodology for Carbon-Nanotube VLSI: Concepts and Experimental Demonstration

IEEE transactions on electron devices, 2009-12, Vol.56 (12), p.2969-2978

2009

Link zum Volltext
IEEE_Xplore

The Future of Hardware Technologies for Computing: N3XT 3D MOSAIC, Illusion Scaleup, Co-Design

2021 IEEE International Electron Devices Meeting (IEDM), 2021, p.25.4.1-25.4.4

2021

Link zum Volltext
IEEE_Xplore

A Physics-Based Compact Model of III-V FETs for Digital Logic Applications: Current-Voltage and Capacitance-Voltage Characteristics

IEEE transactions on electron devices, 2009-12, Vol.56 (12), p.2917-2924

2009

Link zum Volltext
IEEE_Xplore

The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance

IEEE circuits and devices magazine, 2005-01, Vol.21 (1), p.16-26

2005

Link zum Volltext
IEEE_Xplore

Threshold Voltage and On-Off Ratio Tuning for Multiple-Tube Carbon Nanotube FETs

IEEE transactions on nanotechnology, 2009-01, Vol.8 (1), p.4-9

2009

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IEEE_Xplore

Generalized scale length for two-dimensional effects in MOSFETs

IEEE electron device letters, 1998-10, Vol.19 (10), p.385-387

1998

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IEEE_Xplore

An Analytical Derivation of the Density of States, Effective Mass, and Carrier Density for Achiral Carbon Nanotubes

IEEE transactions on electron devices, 2008-01, Vol.55 (1), p.289-297

2008

Link zum Volltext
IEEE_Xplore

Extended Scale Length Theory Targeting Low-Dimensional FETs for Carbon Nanotube FET Digital Logic Design-Technology Co-optimization

2021 IEEE International Electron Devices Meeting (IEDM), 2021, p.27.3.1-27.3.4

2021

Link zum Volltext
IEEE_Xplore

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Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes

Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits

Impact of a Process Variation on Nanowire and Nanotube Device Performance

Electrical characterization of germanium p-channel MOSFETs

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application-Part I: Model of the Intrinsic Channel Region

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application-Part II: Full Device Model and Circuit Performance Benchmarking

Ultralow Voltage Crossbar Nonvolatile Memory Based on Energy-Reversible NEM Switches

Extension and source/drain design for high-performance FinFET devices

Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate

Technology projections of III–V devices down to 11 nm: importance of electrostatics and series resistance

Analysis of Temperature in Phase Change Memory Scaling

Metrics for performance benchmarking of nanoscale Si and carbon nanotube FETs including device nonidealities

Modeling and Analysis of Planar-Gate Electrostatic Capacitance of 1-D FET With Multiple Cylindrical Conducting Channels

Thermal Boundary Resistance Measurements for Phase-Change Memory Devices

Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits

Strained Si CMOS (SS CMOS) technology: opportunities and challenges

Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power Logic

ACCNT-A Metallic-CNT-Tolerant Design Methodology for Carbon-Nanotube VLSI: Concepts and Experimental Demonstration

The Future of Hardware Technologies for Computing: N3XT 3D MOSAIC, Illusion Scaleup, Co-Design

A Physics-Based Compact Model of III-V FETs for Digital Logic Applications: Current-Voltage and Capacitance-Voltage Characteristics

The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance

Threshold Voltage and On-Off Ratio Tuning for Multiple-Tube Carbon Nanotube FETs

Generalized scale length for two-dimensional effects in MOSFETs

An Analytical Derivation of the Density of States, Effective Mass, and Carrier Density for Achiral Carbon Nanotubes

Extended Scale Length Theory Targeting Low-Dimensional FETs for Carbon Nanotube FET Digital Logic Design-Technology Co-optimization

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