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Post-silicon code coverage for multiprocessor system-on-chip designs

IEEE transactions on computers, 2013-02, Vol.62 (2), p.242-246

2013

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Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-01, Vol.36 (1), p.83-96

2017

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Boosting Domain-Specific Debug Through Inter-frame Compression

2022 International Conference on Field-Programmable Technology (ICFPT), 2022, p.1-10

2022

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Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug

ACM transactions on design automation of electronic systems, 2018-12, Vol.23 (6), p.1-25, Article 72

2018

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Adaptive Clock Management of HLS-generated Circuits on FPGAs

ACM transactions on reconfigurable technology and systems, 2022-12, Vol.15 (4), p.1-32, Article 49

2022

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FPGA Architecture Exploration for DNN Acceleration

ACM transactions on reconfigurable technology and systems, 2022-09, Vol.15 (3), p.1-37

2022

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Incremental Trace-Buffer Insertion for FPGA Debug

IEEE transactions on very large scale integration (VLSI) systems, 2014-04, Vol.22 (4), p.850-863

2014

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In-circuit tuning of deep learning designs

Journal of systems architecture, 2021-09, Vol.118, p.102198, Article 102198

2021

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Scalable Signal Selection for Post-Silicon Debug

IEEE transactions on very large scale integration (VLSI) systems, 2013-06, Vol.21 (6), p.1103-1115

2013

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An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug

2018 28th International Conference on Field Programmable Logic and Applications (FPL), 2018, p.403-4037

2018

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Towards Overlay-based Rapid In-Circuit Tuning of Deep Learning Designs

2020 International Conference on Field-Programmable Technology (ICFPT), 2020, p.301-301

2020

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Layout-Aware Embedding for Quantum Annealing Processors

High Performance Computing, p.121-139

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Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays

ACM transactions on reconfigurable technology and systems, 2020-03, Vol.13 (1), p.1-26

2020

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An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating

IEEE transactions on very large scale integration (VLSI) systems, 2016-01, Vol.24 (1), p.178-191

2016

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A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications

ACM transactions on reconfigurable technology and systems, 2008-03, Vol.1 (1), p.1-25

2008

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Floating-Point FPGA: Architecture and Modeling

IEEE transactions on very large scale integration (VLSI) systems, 2009-12, Vol.17 (12), p.1709-1718

2009

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Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network

ACM transactions on design automation of electronic systems, 2014-03, Vol.19 (2), p.1-23

2014

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CACTI: an enhanced cache access and cycle time model

IEEE journal of solid-state circuits, 1996-05, Vol.31 (5), p.677-688

1996

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A detailed power model for field-programmable gate arrays

ACM transactions on design automation of electronic systems, 2005-04, Vol.10 (2), p.279-302

2005

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Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-05, Vol.29 (5), p.816-829

2010

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Optimizing Floating Point Units in Hybrid FPGAs

IEEE transactions on very large scale integration (VLSI) systems, 2012-07, Vol.20 (7), p.1295-1303

2012

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An Analytical Model Relating FPGA Architecture to Logic Density and Depth

IEEE transactions on very large scale integration (VLSI) systems, 2011-12, Vol.19 (12), p.2229-2242

2011

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GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering

IEEE transactions on very large scale integration (VLSI) systems, 2008-11, Vol.16 (11), p.1521-1534

2008

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Towards development of an analytical model relating FPGA architecture parameters to routability

ACM transactions on reconfigurable technology and systems, 2013-07, Vol.6 (2), p.1-24

2013

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Formal-Analysis-Based Trace Computation for Post-Silicon Debug

IEEE transactions on very large scale integration (VLSI) systems, 2012-11, Vol.20 (11), p.1997-2010

2012

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Post-silicon code coverage for multiprocessor system-on-chip designs

Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits

Boosting Domain-Specific Debug Through Inter-frame Compression

Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug

Adaptive Clock Management of HLS-generated Circuits on FPGAs

FPGA Architecture Exploration for DNN Acceleration

Incremental Trace-Buffer Insertion for FPGA Debug

In-circuit tuning of deep learning designs

Scalable Signal Selection for Post-Silicon Debug

An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug

Towards Overlay-based Rapid In-Circuit Tuning of Deep Learning Designs

Layout-Aware Embedding for Quantum Annealing Processors

Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays

An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating

A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications

Floating-Point FPGA: Architecture and Modeling

Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network

CACTI: an enhanced cache access and cycle time model

A detailed power model for field-programmable gate arrays

Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm

Optimizing Floating Point Units in Hybrid FPGAs

An Analytical Model Relating FPGA Architecture to Logic Density and Depth

GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering

Towards development of an analytical model relating FPGA architecture parameters to routability

Formal-Analysis-Based Trace Computation for Post-Silicon Debug

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