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Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

IEEE journal of solid-state circuits, 2009-01, Vol.44 (1), p.49-63

2009

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A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance

IEEE journal of solid-state circuits, 2011-01, Vol.46 (1), p.194-208

2011

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IEEE_Xplore

Path confidence based lookahead prefetching

2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2016, p.1-12

2016

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IEEE_Xplore

Transparent Hardware Management of Stacked DRAM as Part of Memory

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014, p.13-24

2014

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IEEE_Xplore

CHAMELEON: a dynamically reconfigurable heterogeneous memory system

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2018, p.533-545

2018

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IEEE_Xplore

Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors

IEEE transactions on very large scale integration (VLSI) systems, 2009-12, Vol.17 (12), p.1679-1690

2009

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IEEE_Xplore

Improving cache lifetime reliability at ultra-low voltages

2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2009, p.89-99

2009

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IEEE_Xplore

Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

Computer architecture news, , Vol.36 (3), p.203-214

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Improving cache performance using read-write partitioning

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), 2014, p.452-463

2014

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IEEE_Xplore

Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors

Computer architecture news, 2014, Vol.42 (3), p.361-372

2014

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Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), 2014, p.361-372

2014

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IEEE_Xplore

An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms

Proceedings of the 40th Annual International Symposium on computer architecture, 2013, p.60-71

2013

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Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors

International Symposium on Low Power Electronics and Design: Proceedings of the 2007 international symposium on Low power electronics and design; 27-29 Aug. 2007, 2007, p.50-55

2007

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Detecting and mitigating data-dependent DRAM failures by exploiting current memory content

2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2017, p.27-40

2017

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IEEE_Xplore

Improving DRAM performance by parallelizing refreshes with accesses

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), 2014, p.356-367

2014

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IEEE_Xplore

Efficient Machine Learning on Encrypted Data Using Hyperdimensional Computing

2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2023, p.1-6

2023

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Reducing cache power with low-cost, multi-bit error-correcting codes

Proceedings of the 37th annual international symposium on computer architecture, 2010, p.83-93

2010

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The heterogeneous block architecture

2014 IEEE 32nd International Conference on Computer Design (ICCD), 2014, p.386-393

2014

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Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy

Operating systems review, 2017-04, Vol.51 (2), p.737-749

2017

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A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM

IEEE computer architecture letters, 2017-07, Vol.16 (2), p.88-93

2017

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IEEE_Xplore

Energy-efficient cache design using variable-strength error-correcting codes

2011 38th Annual International Symposium on Computer Architecture (ISCA), 2011, p.461-472

2011

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IEEE_Xplore

MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012, p.305-316

2012

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IEEE_Xplore

Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), 2014, p.626-637

2014

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IEEE_Xplore

Adaptive Cache Design to Enable Reliable Low-Voltage Operation

IEEE transactions on computers, 2011-01, Vol.60 (1), p.50-63

2011

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IEEE_Xplore

159 Antiplatelet Therapy After Traumatic Intracranial Hemorrhage

Neurosurgery, 2014-08, Vol.61 (CN_suppl_1), p.212-212

2014

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Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance

Path confidence based lookahead prefetching

Transparent Hardware Management of Stacked DRAM as Part of Memory

CHAMELEON: a dynamically reconfigurable heterogeneous memory system

Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors

Improving cache lifetime reliability at ultra-low voltages

Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

Improving cache performance using read-write partitioning

Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors

Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors

An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms

Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors

Detecting and mitigating data-dependent DRAM failures by exploiting current memory content

Improving DRAM performance by parallelizing refreshes with accesses

Efficient Machine Learning on Encrypted Data Using Hyperdimensional Computing

Reducing cache power with low-cost, multi-bit error-correcting codes

The heterogeneous block architecture

Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy

A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM

Energy-efficient cache design using variable-strength error-correcting codes

MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP

Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers

Adaptive Cache Design to Enable Reliable Low-Voltage Operation

159 Antiplatelet Therapy After Traumatic Intracranial Hemorrhage

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