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Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults-From Device to Circuit Level

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-04, Vol.35 (4), p.586-597

2016

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Dynamic Switch Migration in Distributed Software-Defined Networks to Achieve Controller Load Balance

IEEE journal on selected areas in communications, 2019-03, Vol.37 (3), p.515-529

2019

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Thermal-Constrained Task Scheduling on 3-D Multicore Processors for Throughput-and-Energy Optimization

IEEE transactions on very large scale integration (VLSI) systems, 2015-11, Vol.23 (11), p.2719-2723

2015

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CASSER: A Closed-Form Analysis Framework for Statistical Soft Error Rate

IEEE transactions on very large scale integration (VLSI) systems, 2013-10, Vol.21 (10), p.1837-1848

2013

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Hierarchical Cooperation and Load Balancing for Scalable Autonomous Vehicle Routing in Multi-Access Edge Computing Environment

IEEE transactions on vehicular technology, 2023-06, Vol.72 (6), p.1-13

2023

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Accurate performance evaluation of VLSI designs with selected CMOS process parameters

IET circuits, devices & systems, 2018-01, Vol.12 (1), p.116-123

2018

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Demystifying Iddq Data With Process Variation for Automatic Chip Classification

IEEE transactions on very large scale integration (VLSI) systems, 2015-06, Vol.23 (6), p.1175-1179

2015

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DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction

IEEE transactions on very large scale integration (VLSI) systems, 2020-04, Vol.28 (4), p.1030-1042

2020

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Unleashing Parallelism With Minimal Test Inflation in Multi-Threaded Test Pattern Generation

IEEE access, 2018-01, Vol.6, p.49269-49281

2018

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A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability

ACM transactions on design automation of electronic systems, 2021-11, Vol.26 (6), p.1-12

2021

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Speeding Up Functional Timing Analysis by Concise Formulation of Timed Characteristic Functions

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.5281-5294

2020

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P4SF: A High-Performance Stateful Firewall on Commodity P4-Programmable Switch

NOMS 2022-2022 IEEE/IFIP Network Operations and Management Symposium, 2022, p.1-5

2022

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Real-Time In-Network Microburst Mitigation on Programmable Switch

IEEE access, 2022, Vol.10, p.2446-2456

2022

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Fast Scan-Chain Ordering for 3-D-IC Designs Under Through-Silicon-Via (TSV) Constraints

IEEE transactions on very large scale integration (VLSI) systems, 2013-06, Vol.21 (6), p.1170-1174

2013

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Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65nm CMOS Technologies

2022 IEEE International Test Conference (ITC), 2022, p.128-136

2022

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Generating Layouts of Standard Cells by Implicit Learning on Design Rules for Advanced Processes

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, p.1829-1834

2021

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TA-FTA: transition-aware functional timing analysis with a four-valued encoding

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6

2015

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P4-TPG: Accelerating Deterministic Parallel Test Pattern Generation by Preemptive, Proactive, and Preventive Schedulings

IEEE access, 2019, Vol.7, p.6816-6830

2019

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An online thermal-constrained task scheduler for 3D multi-core processors

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, p.351-356

2015

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Rad-Hard Designs by Automated Latching-Delay Assignment and Time-Borrowable D-Flip-Flop

IEEE transactions on computers, 2022-05, Vol.71 (5), p.1008-1020

2022

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A General and Automatic Cell Layout Generation Framework With Implicit Learning on Design Rules

IEEE transactions on very large scale integration (VLSI) systems, 2022-09, Vol.30 (9), p.1341-1354

2022

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Assessing the impact of communication delays for Autonomous Intersection Management systems

Vehicular Communications, 2024-10, Vol.49, p.100829, Article 100829

2024

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A Determinate Radiation Hardened Technique for Safety-Critical CMOS Designs

Journal of electronic testing, 2015-04, Vol.31 (2), p.181-192

2015

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SWF: Segmented Wildcard Forwarding for flow migration in OpenFlow datacenter networks

2015 IEEE International Conference on Communications (ICC), 2015, p.313-318

2015

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Fast-yet-accurate variation-aware current and voltage modelling of radiation-induced transient fault

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, p.211-216

2016

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Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults-From Device to Circuit Level

Dynamic Switch Migration in Distributed Software-Defined Networks to Achieve Controller Load Balance

Thermal-Constrained Task Scheduling on 3-D Multicore Processors for Throughput-and-Energy Optimization

CASSER: A Closed-Form Analysis Framework for Statistical Soft Error Rate

Hierarchical Cooperation and Load Balancing for Scalable Autonomous Vehicle Routing in Multi-Access Edge Computing Environment

Accurate performance evaluation of VLSI designs with selected CMOS process parameters

Demystifying Iddq Data With Process Variation for Automatic Chip Classification

DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction

Unleashing Parallelism With Minimal Test Inflation in Multi-Threaded Test Pattern Generation

A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability

Speeding Up Functional Timing Analysis by Concise Formulation of Timed Characteristic Functions

P4SF: A High-Performance Stateful Firewall on Commodity P4-Programmable Switch

Real-Time In-Network Microburst Mitigation on Programmable Switch

Fast Scan-Chain Ordering for 3-D-IC Designs Under Through-Silicon-Via (TSV) Constraints

Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65nm CMOS Technologies

Generating Layouts of Standard Cells by Implicit Learning on Design Rules for Advanced Processes

TA-FTA: transition-aware functional timing analysis with a four-valued encoding

P4-TPG: Accelerating Deterministic Parallel Test Pattern Generation by Preemptive, Proactive, and Preventive Schedulings

An online thermal-constrained task scheduler for 3D multi-core processors

Rad-Hard Designs by Automated Latching-Delay Assignment and Time-Borrowable D-Flip-Flop

A General and Automatic Cell Layout Generation Framework With Implicit Learning on Design Rules

Assessing the impact of communication delays for Autonomous Intersection Management systems

A Determinate Radiation Hardened Technique for Safety-Critical CMOS Designs

SWF: Segmented Wildcard Forwarding for flow migration in OpenFlow datacenter networks

Fast-yet-accurate variation-aware current and voltage modelling of radiation-induced transient fault

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