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Charge-mediated voltage modulation of magnetism in Hf0.5Zr0.5O2/Co multiferroic heterojunction

Chinese physics B, 2023-02, Vol.32 (2), p.541-546

2023

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Self-Selection RRAM Cell With Sub- \mu \text Switching Current and Robust Reliability Fabricated by High- K /Metal Gate CMOS Compatible Technology

IEEE transactions on electron devices, 2016-11, Vol.63 (11), p.4295-4301

2016

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Jet microchannel with sawtooth wall for efficient cooling of high-power electronics

International journal of heat and mass transfer, 2023-06, Vol.206, p.123955, Article 123955

2023

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Transient-Liquid-Phase Bonding of Granulated Cu-Sn Bumps With a 4-μm Fine Pitch

IEEE transactions on electron devices, 2023-02, Vol.70 (2), p.683-688

2023

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Capacitance Modeling With Charge Partitions Covering Full-Region Operations of TFETs

IEEE transactions on electron devices, 2024-07, Vol.71 (7), p.4373-4380

2024

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Novel Channel-First Fishbone FETs With Symmetrical Threshold Voltages and Balanced Driving Currents Using Single Work Function Metal Process

IEEE transactions on electron devices, 2022-11, Vol.69 (11), p.1-7

2022

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A Surface Potential Based Full-Region Current Model for Doping Segregated TFETs

IEEE transactions on electron devices, 2024-01, Vol.71 (1), p.1-8

2024

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Fabrication of High‐Density Micro‐Bump Arrays for 3D Integration of MEMS and CMOS

IEEJ transactions on electrical and electronic engineering, 2024-05, Vol.19 (5), p.785-790

2024

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Fully Hardware Memristive Neuromorphic Computing Enabled by the Integration of Trainable Dendritic Neurons and High‐Density RRAM Chip

Advanced functional materials, 2024-10, Vol.34 (44), p.n/a

2024

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The fabrication of spin transfer torque-based magnetoresistive random access memory cell with ultra-low switching power

Japanese Journal of Applied Physics, 2024-05, Vol.63 (5), p.5

2024

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Bonding of 5 μm Cu-Sn Micro Bumps Using Thermal Reflow and Solid-State Pre-Bonding

IEEE transactions on components, packaging, and manufacturing technology (2011), 2022-10, Vol.12 (10), p.1-1

2022

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Experimental Investigation of Ultrathin Al₂O₃ Ex-Situ Interfacial Doping Strategy on Laminated HKMG Stacks via ALD

IEEE transactions on electron devices, 2022-04, Vol.69 (4), p.1964-1971

2022

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Layout Optimization of Complementary FET 6T-SRAM Cell Based on a Universal Methodology Using Sensitivity With Respect to Parasitic - and -Values

IEEE transactions on electron devices, 2022-11, Vol.69 (11), p.6095-6101

2022

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Layout Optimization of Complementary FET 6T-SRAM Cell Based on a Universal Methodology Using Sensitivity With Respect to Parasitic \textit -and \textit -Values

IEEE transactions on electron devices, 2022, p.1-7

2022

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A Novel CMOS FEOL-Embedded Asymmetrical FET for Capacitor-less and Long-Retention DRAM Based on 300mm Logic Foundry Platform

2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024, p.13-16

2024

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Heat transfer performance study of fluid rotating microchannel heat sink

Case studies in thermal engineering, 2024-06, Vol.58, p.104390, Article 104390

2024

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Highly efficient voltage-controlled magnetism in HfZrO/CoFeB hybrid film and Hall device

Japanese Journal of Applied Physics, 2022-08, Vol.61 (SJ), p.SJ1006

2022

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Charge-mediated voltage modulation of magnetism in Hf 0.5 Zr 0.5 O 2 /Co multiferroic heterojunction

Chinese physics B, 2023-02, Vol.32 (2), p.27504

2023

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A novel source/drain on void (SDOV) MOSFET implemented by local co-implantation of hydrogen and helium

Microelectronic engineering, 2008-07, Vol.85 (7), p.1490-1494

2008

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Scaling capability improvement of silicon-on-void (SOV) MOSFET

Semiconductor science and technology, 2005-02, Vol.20 (2), p.115-119

2005

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A scalable universal Ising machine based on interaction-centric storage and compute-in-memory

Nature electronics, 2024-08, Vol.7 (10), p.904-913

2024

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First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology

ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC), 2023, p.13-16

2023

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First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap

2015 IEEE International Electron Devices Meeting (IEDM), 2015, p.22.2.1-22.2.4

2015

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Deep insights into dielectric breakdown in tunnel FETs with awareness of reliability and performance co-optimization

2016 IEEE International Electron Devices Meeting (IEDM), 2016, p.31.5.1-31.5.4

2016

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Adding the missing time-dependent layout dependency into device-circuit-layout co-optimization - New findings on the layout dependent aging effects

2015 IEEE International Electron Devices Meeting (IEDM), 2015, p.11.7.1-11.7.4

2015

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Charge-mediated voltage modulation of magnetism in Hf0.5Zr0.5O2/Co multiferroic heterojunction

Self-Selection RRAM Cell With Sub- \mu \text Switching Current and Robust Reliability Fabricated by High- K /Metal Gate CMOS Compatible Technology

Jet microchannel with sawtooth wall for efficient cooling of high-power electronics

Transient-Liquid-Phase Bonding of Granulated Cu-Sn Bumps With a 4-μm Fine Pitch

Capacitance Modeling With Charge Partitions Covering Full-Region Operations of TFETs

Novel Channel-First Fishbone FETs With Symmetrical Threshold Voltages and Balanced Driving Currents Using Single Work Function Metal Process

A Surface Potential Based Full-Region Current Model for Doping Segregated TFETs

Fabrication of High‐Density Micro‐Bump Arrays for 3D Integration of MEMS and CMOS

Fully Hardware Memristive Neuromorphic Computing Enabled by the Integration of Trainable Dendritic Neurons and High‐Density RRAM Chip

The fabrication of spin transfer torque-based magnetoresistive random access memory cell with ultra-low switching power

Bonding of 5 μm Cu-Sn Micro Bumps Using Thermal Reflow and Solid-State Pre-Bonding

Experimental Investigation of Ultrathin Al₂O₃ Ex-Situ Interfacial Doping Strategy on Laminated HKMG Stacks via ALD

Layout Optimization of Complementary FET 6T-SRAM Cell Based on a Universal Methodology Using Sensitivity With Respect to Parasitic - and -Values

Layout Optimization of Complementary FET 6T-SRAM Cell Based on a Universal Methodology Using Sensitivity With Respect to Parasitic \textit -and \textit -Values

A Novel CMOS FEOL-Embedded Asymmetrical FET for Capacitor-less and Long-Retention DRAM Based on 300mm Logic Foundry Platform

Heat transfer performance study of fluid rotating microchannel heat sink

Highly efficient voltage-controlled magnetism in HfZrO/CoFeB hybrid film and Hall device

Charge-mediated voltage modulation of magnetism in Hf 0.5 Zr 0.5 O 2 /Co multiferroic heterojunction

A novel source/drain on void (SDOV) MOSFET implemented by local co-implantation of hydrogen and helium

Scaling capability improvement of silicon-on-void (SOV) MOSFET

A scalable universal Ising machine based on interaction-centric storage and compute-in-memory

First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology

First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap

Deep insights into dielectric breakdown in tunnel FETs with awareness of reliability and performance co-optimization

Adding the missing time-dependent layout dependency into device-circuit-layout co-optimization - New findings on the layout dependent aging effects

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