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A 0.13 [Formula Omitted]m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

IEEE journal of solid-state circuits, 2009-05, Vol.44 (5), p.1454-1463

2009

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0.13-[mu]m RF CMOS and varactors performance optimization by multiple gate layouts

IEEE transactions on electron devices, 2004-12, Vol.51 (12), p.2181

2004

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0.13-μm RF CMOS and varactors performance optimization by multiple gate layouts

IEEE transactions on electron devices, 2004-12, Vol.51 (12), p.2181-2185

2004

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0.13-mum RF CMOS and varactors performance optimization by multiple gate layouts

IEEE transactions on electron devices, 2004-12, Vol.51 (12), p.2181-2185

2004

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0.13-/spl mu/m RF CMOS and varactors performance optimization by multiple gate layouts

IEEE transactions on electron devices, 2004-12, Vol.51 (12), p.2181-2185

2004

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A 0.13 \mu m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

IEEE journal of solid-state circuits, 2009-05, Vol.44 (5), p.1454-1463

2009

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A 0.18 μm p-MOSFET large-signal RF model and its application on MMIC design

Solid-state electronics, 2003-06, Vol.47 (6), p.1117-1122

2003

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A 0.18 /spl mu/m CMOS receiver for 3.1 to 10.6GHz MB-OFDM UWB communication systems

IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006, 2006, p.4 pp.-264

2006

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0.18um BCD technology with best-in-class LDMOS from 6 V to 45 V

2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2014, p.179-181

2014

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A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010, p.266-267

2010

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A 0.35- Delta mm CMOS cross-coupled complementary Colpitts voltage controlled oscillator

Microwave and optical technology letters, 2011-09, Vol.53 (9), p.2189-2192

2011

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A 0.35-μm CMOS cross-coupled complementary Colpitts voltage controlled oscillator

Microwave and optical technology letters, 2011-09, Vol.53 (9), p.2189-2192

2011

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A 0.35 μm CMOS divide-by-2 quadrature injection-locked frequency divider based on voltage–current feedback topology

Microelectronics and reliability, 2010-05, Vol.50 (5), p.594-598

2010

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A 0.35 μm CMOS divide-by-2 quadrature injection-locked frequency divider based on voltage―current feedback topology: 2009 International Electron Devices and Materials Symposium (IEDMS)

Microelectronics and reliability, 2010, Vol.50 (5), p.594-598

2010

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0.35 μm CMOS–MEMS low-mechanical-noise micro accelerometer

Microsystem technologies : sensors, actuators, systems integration, 2018, Vol.24 (1), p.299-304

2018

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A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications

IEEE journal of solid-state circuits, 2016-01, Vol.51 (1), p.56-67

2016

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A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process

Microelectronics, 2011-01, Vol.42 (1), p.43-51

2011

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A 0.5 V 320 MHz 8 bitx8 bit pipelined multiplier in 130 nm CMOS process

Microelectronics, 2011-01, Vol.42 (1), p.43-51

2011

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A 0.5V 320MHz 8bit×8bit pipelined multiplier in 130nm CMOS process

Microelectronics, 2011-01, Vol.42 (1), p.43-51

2011

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A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time

2012 IEEE International Solid-State Circuits Conference, 2012, p.434-436

2012

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A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction

2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2019, p.33-34

2019

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A 0.64 mm 2 Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction

IEEE transactions on very large scale integration (VLSI) systems, 2011-11, Vol.19 (11), p.1937-1948

2011

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A 0.64 mm ^ Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction

IEEE transactions on very large scale integration (VLSI) systems, 2011-11, Vol.19 (11), p.1937-1948

2011

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A 0.64 mm2 Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction

IEEE transactions on very large scale integration (VLSI) systems, 2011, Vol.19 (11), p.1937-1948

2011

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A 0.8 V 80.3 dB SNDR stage-shared ΔΣ modulator with chopper-embedded switched-opamp for biomedical application

2012 IEEE Asian Solid State Circuits Conference (A-SSCC), 2012, p.253-256

2012

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1 – 25 von 31.265

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A 0.13 [Formula Omitted]m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

0.13-[mu]m RF CMOS and varactors performance optimization by multiple gate layouts

0.13-μm RF CMOS and varactors performance optimization by multiple gate layouts

0.13-mum RF CMOS and varactors performance optimization by multiple gate layouts

0.13-/spl mu/m RF CMOS and varactors performance optimization by multiple gate layouts

A 0.13 \mu m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

A 0.18 μm p-MOSFET large-signal RF model and its application on MMIC design

A 0.18 /spl mu/m CMOS receiver for 3.1 to 10.6GHz MB-OFDM UWB communication systems

0.18um BCD technology with best-in-class LDMOS from 6 V to 45 V

A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications

A 0.35- Delta mm CMOS cross-coupled complementary Colpitts voltage controlled oscillator

A 0.35-μm CMOS cross-coupled complementary Colpitts voltage controlled oscillator

A 0.35 μm CMOS divide-by-2 quadrature injection-locked frequency divider based on voltage–current feedback topology

A 0.35 μm CMOS divide-by-2 quadrature injection-locked frequency divider based on voltage―current feedback topology: 2009 International Electron Devices and Materials Symposium (IEDMS)

0.35 μm CMOS–MEMS low-mechanical-noise micro accelerometer

A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications

A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process

A 0.5 V 320 MHz 8 bitx8 bit pipelined multiplier in 130 nm CMOS process

A 0.5V 320MHz 8bit×8bit pipelined multiplier in 130nm CMOS process

A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time

A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction

A 0.64 mm 2 Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction

A 0.64 mm ^ Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction

A 0.64 mm2 Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction

A 0.8 V 80.3 dB SNDR stage-shared ΔΣ modulator with chopper-embedded switched-opamp for biomedical application

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