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256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers
IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.210-217
2017
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Effects of Localized Body Doping on Switching Characteristics of Tunnel FET Inverters With Vertical Structures
IEEE transactions on electron devices, 2017-04, Vol.64 (4), p.1799-1805
2017
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Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray
IEEE transactions on electron devices, 2012-01, Vol.59 (1), p.35-45
2012
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Analysis on Program Disturbance in Channel-Stacked NAND Flash Memory With Layer Selection by Multilevel Operation
IEEE transactions on electron devices, 2016-03, Vol.63 (3), p.1041-1046
2016
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Analysis on Trapping Kinetics of Stress-Induced Trapped Holes in Gate Dielectric of Amorphous HfInZnO TFT
IEEE transactions on electron devices, 2016-06, Vol.63 (6), p.2398-2404
2016
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Multi-Level Threshold Voltage Setting Method of String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory
IEEE electron device letters, 2015-12, Vol.36 (12), p.1318-1320
2015
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Novel Program Method of String Select Transistors for Layer Selection in Channel-Stacked NAND Flash Memory
IEEE transactions on electron devices, 2016-09, Vol.63 (9), p.3521-3526
2016
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Light Effect on Negative Bias-Induced Instability of HfInZnO Amorphous Oxide Thin-Film Transistor
IEEE transactions on electron devices, 2011-04, Vol.58 (4), p.1127-1133
2011
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Layer Selection by Multi-Level Permutation in 3-D Stacked NAND Flash Memory
IEEE electron device letters, 2016-07, Vol.37 (7), p.866-869
2016
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Channel-Stacked NAND Flash Memory With Tied Bit-Line and Ground Select Transistor
IEEE electron device letters, 2016-11, Vol.37 (11), p.1418-1421
2016
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Temperature effect on negative bias-induced instability of HfInZnO amorphous oxide thin film transistor
Applied physics letters, 2011-02, Vol.98 (6), p.063502-063502-3
2011
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Vertical-Channel STacked ARray (VCSTAR) for 3D NAND flash memory
Solid-state electronics, 2012-12, Vol.78, p.34-38
2012
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Variation of Threshold Voltage and ON-Cell Current Caused by Cell Gate Length Fluctuation in Virtual Source/Drain NAND Flash Memory
Japanese Journal of Applied Physics, 2012-07, Vol.51 (7), p.074301-074301-6
2012
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Enhancement of Radiative Recombination by Different Indium Composition of Multiple Quantum Barriers in GaN-Based Light-Emitting Diodes
Japanese Journal of Applied Physics, 2013-06, Vol.52 (6), p.06GE04-06GE04-5
2013
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Arch NAND Flash Memory Array With Improved Virtual Source/Drain Performance
IEEE electron device letters, 2010-12, Vol.31 (12), p.1374-1376
2010
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Stacked Gated Twin-Bit (SGTB) SONOS Memory Device for High-Density Flash Memory
IEEE transactions on nanotechnology, 2012-03, Vol.11 (2), p.307-313
2012
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Variation of Threshold Voltage and ON-Cell Current Caused by Cell Gate Length Fluctuation in Virtual Source/Drain NAND Flash Memory
Japanese Journal of Applied Physics, 2012-07, Vol.51 (7R), p.74301
2012
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A Vertical 4-Bit SONOS Flash Memory and a Unique 3-D Vertical nor Array Structure
IEEE transactions on nanotechnology, 2010-01, Vol.9 (1), p.70-77
2010
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Investigation of Threshold Voltage Disturbance Caused by Programmed Adjacent Cell in Virtual Source/Drain NAND Flash Memory
Japanese Journal of Applied Physics, 2011-04, Vol.50 (4S), p.4
2011
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Extended Word-Line NAND Flash Memory
Japanese Journal of Applied Physics, 2009-08, Vol.48 (8), p.81203
2009
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Investigation of Threshold Voltage Disturbance Caused by Programmed Adjacent Cell in Virtual Source/Drain NAND Flash Memory
Japanese Journal of Applied Physics, 2011-04, Vol.50 (4), p.04DD08-04DD08-4
2011
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A study on gate-AU-around (GAA) polycrystalline silicon channel SONOS flash memory
2013 IEEE 5th International Nanoelectronics Conference (INEC), 2013, p.69-71
2013
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Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories
Japanese Journal of Applied Physics, 2010-08, Vol.49 (8), p.084301-084301-4
2010
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Channel-stacked NAND flash memory with layer selection by multi-level operation (LSM)
2013 IEEE International Electron Devices Meeting, 2013, p.3.8.1-3.8.4
2013
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7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers
2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, p.130-131
2016
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