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Growth and characterization of atomic layer deposited WC0.7N0.3 on polymer films

Journal of applied physics, 2004-01, Vol.95 (1), p.381-388

2004

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Integrating ENSEMBLE™ PMD low- k at the PMD level of CMOS logic circuits

Microelectronic engineering, 2006-11, Vol.83 (11), p.2303-2308

2006

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Barrier studies on porous silk semiconductor dielectric

Microelectronic engineering, 2003-11, Vol.70 (2), p.352-357

2003

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Development of a hybrid CVD/SOD integration sequence for reliable, high performance interconnect systems

Microelectronic engineering, 2004-10, Vol.76 (1-4), p.46-51

2004

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In-Situ Low Energy Ion Milling with a FIB-SEM for TEM lift-out Sample Preparation of Copper Damascene Structures Fabricated with Low k porous SiLKTM Semiconductor Dielectric

Microscopy and microanalysis, 2003-08, Vol.9 (S02), p.874-875

2003

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Sequential Process Modeling for Determining Process-Induced Thermal Stress in Advanced Cu/Low-k Interconnects

MRS proceedings, 2003, Vol.766, Article E6.2

2003

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Automated Sample Preparation of Low-k Dielectrics for FESEM

Microscopy and microanalysis, 2005-08, Vol.11 (S02), p.2108-2109

2005

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Air Bridge Technology: A Comparison of Novel Interconnect Materials and Integration Schemes for Beyond 45 nm

MRS proceedings, 2003, Vol.766, Article E5.3

2003

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In-Situ Low Energy Ion Milling with a FIB-SEM for TEM lift-out Sample Preparation of Copper Damascene Structures Fabricated with Low k porous SiLK TM Semiconductor Dielectric

Microscopy and microanalysis, 2003-08, Vol.9 (S02), p.874-875

2003

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Post patterning meso porosity creation: a potential solution for pore sealing

Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695), 2003, p.242-244

2003

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Development of a hybrid CVD/SOD integration sequence for reliable, high performance interconnect systems

2004 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (IEEE Cat. No.04CH37530), 2004, p.433-436

2004

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Reliability Characterization of Different Pore Sealing Techniques on Porous Silk Dielectric Films

2006 IEEE International Reliability Physics Symposium Proceedings, 2006, p.496-501

2006

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Process integration induced thermodesorption from SiO2/SiLK resin dielectric based interconnects

Journal of vacuum science & technology. B, Microelectronics and nanometer structures processing, measurement and phenomena, 1999-09, Vol.17 (5), p.2136-2146

1999

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Integration of unlanded via in a non-etchback SOG direct-on-metal approach in 0.25 micron CMOS process

Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102), 1998, p.45-47

1998

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Etch process development for FLARE for dual damascene architecture using a N2/O2 plasma

1999

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Surface characterization of a low dielectric constant polymer–SiLK polymer, and investigation of its interface with Cu

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 1999-09, Vol.17 (5), p.2336-2340

1999

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Integration feasibility of porous SiLK semiconductor dielectric

Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461), 2001, p.253-254

2001

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Multi-Level Air Gap Integration for 32/22nm nodes using a Spin-on Thermal Degradable Polymer and a SiOC CVD Hard Mask

2007 IEEE International Interconnect Technology Conferencee, 2007, p.61-63

2007

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A fourth material: thermally stable organic gap-fill spin-on-polymer enabling new integration concepts [DRAM example]

IEEE International Electron Devices Meeting 2003, 2003, p.28.4.1-28.4.4

2003

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Process integration induced thermodesorption from SiO 2 /SiLK resin dielectric based interconnects

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 1999-09, Vol.17 (5), p.2136-2146

1999

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Etch process development for FLARE/sup TM/ for dual damascene architecture using a N/sub 2//O/sub 2/ plasma

Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247), 1999, p.59-61

1999

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Integration of a low permittivity spin-on embedded hardmask for Cu/SiLK resin dual damascene

Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461), 2001, p.60-62

2001

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Une charte européenne de l'énergie: pour quoi faire?

Revue du Marche Commun et de l'Union Europeenne, 1991-06, p.439-445

Waeterloos, Christian

1991

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Growth and characterization of atomic layer deposited WC0.7N0.3 on polymer films

Integrating ENSEMBLE™ PMD low- k at the PMD level of CMOS logic circuits

Barrier studies on porous silk semiconductor dielectric

Development of a hybrid CVD/SOD integration sequence for reliable, high performance interconnect systems

In-Situ Low Energy Ion Milling with a FIB-SEM for TEM lift-out Sample Preparation of Copper Damascene Structures Fabricated with Low k porous SiLKTM Semiconductor Dielectric

Sequential Process Modeling for Determining Process-Induced Thermal Stress in Advanced Cu/Low-k Interconnects

Automated Sample Preparation of Low-k Dielectrics for FESEM

Air Bridge Technology: A Comparison of Novel Interconnect Materials and Integration Schemes for Beyond 45 nm

In-Situ Low Energy Ion Milling with a FIB-SEM for TEM lift-out Sample Preparation of Copper Damascene Structures Fabricated with Low k porous SiLK TM Semiconductor Dielectric

Post patterning meso porosity creation: a potential solution for pore sealing

Development of a hybrid CVD/SOD integration sequence for reliable, high performance interconnect systems

Reliability Characterization of Different Pore Sealing Techniques on Porous Silk Dielectric Films

Process integration induced thermodesorption from SiO2/SiLK resin dielectric based interconnects

Integration of unlanded via in a non-etchback SOG direct-on-metal approach in 0.25 micron CMOS process

Etch process development for FLARE for dual damascene architecture using a N2/O2 plasma

Surface characterization of a low dielectric constant polymer–SiLK polymer, and investigation of its interface with Cu

Integration feasibility of porous SiLK semiconductor dielectric

Multi-Level Air Gap Integration for 32/22nm nodes using a Spin-on Thermal Degradable Polymer and a SiOC CVD Hard Mask

A fourth material: thermally stable organic gap-fill spin-on-polymer enabling new integration concepts [DRAM example]

Process integration induced thermodesorption from SiO 2 /SiLK resin dielectric based interconnects

Etch process development for FLARE/sup TM/ for dual damascene architecture using a N/sub 2//O/sub 2/ plasma

Integration of a low permittivity spin-on embedded hardmask for Cu/SiLK resin dual damascene

Une charte européenne de l'énergie: pour quoi faire?

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