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A 0.1e- vertical FPN 4.7e- read noise 71dB DR CMOS image sensor with 13b column-parallel single-ended cyclic ADCs

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.268-269,269a

2009

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IEEE_Xplore

A 0.2-/spl mu/m bipolar-CMOS technology on bonded SOI with copper metallization for ultra high-speed processors

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217), 1998, p.209-212

1998

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IEEE_Xplore

0.29-/spl mu/m/sup 2/ trench cell technologies for 1G-bit DRAMs with open/folded-bit-line layout and selective growth technique

1995 Symposium on VLSI Technology. Digest of Technical Papers, 1995, p.137-138

1995

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IEEE_Xplore

A 0.35 /spl mu/m ECL-CMOS process technology on SOI for 1 ns mega-bits SRAMs with 40 ps gate array

Proceedings of International Electron Devices Meeting, 1995, p.923-926

1995

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IEEE_Xplore

A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW

2012 Symposium on VLSI Circuits (VLSIC), 2012, p.194-195

2012

Link zum Volltext
IEEE_Xplore

0.5- mu m 2 M-transistor BiPNMOS channelless gate array

IEEE journal of solid-state circuits, 1991-11, Vol.26 (11), p.1615-1620

1991

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IEEE_Xplore

0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file

IEEE journal of solid-state circuits, 1992-11, Vol.27 (11), p.1579-1584

1992

Link zum Volltext
IEEE_Xplore

0.5-mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache andten-port register file

IEEE journal of solid-state circuits, 1992-11, Vol.27 (11), p.1579-1584

1992

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0.5 mu m BiCMOS standard-cell macros including 0.5 W 3 ns register file and 0.6 W 5 ns 32 kB cache

1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 1992, p.46-47

1992

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IEEE_Xplore

0.5/spl mu/m 2M-transistor BipnMOS Channelless Gate Array

1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1991, p.148-307

1991

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IEEE_Xplore

A 0.5 V 200 MHz 1-stage 32 b ALU using a body bias controlled SOI pass-gate logic

1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers, 1997, Vol.40, p.286-287

1997

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IEEE_Xplore

0.5 V SOI CMOS pass-gate logic

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC, 1996, p.88-89

1996

Link zum Volltext
IEEE_Xplore

0.5-μm 2M-transistor BiPNMOS channelless gate array

IEEE journal of solid-state circuits, 1991-11, Vol.26 (11), p.1615-1620

1991

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0.5-μm 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file : Memory and logic

IEEE journal of solid-state circuits, 1992, Vol.27 (11), p.1579-1584

1992

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Verfügbarkeit prüfen

A 0.5 μm BiCMOS channelless gate array

1989 Proceedings of the IEEE Custom Integrated Circuits Conference, 1989, p.8.7/1-8.7/4

1989

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0.6 /spl mu/m BiCMOS based 15 and 25 V LDMOS for analog applications

Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD '01 (IEEE Cat. No.01CH37216), 2001, p.169-172

2001

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IEEE_Xplore

A 0.602 /spl mu/m/sup 2/ nestled 'Chain' cell structure formed by one mask etching process for 64 Mbit FeRAM

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004, 2004, p.150-151

2004

Link zum Volltext
IEEE_Xplore

A 0.7-mW/2-GHz dual modulus prescaler IC

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94, 1994, p.391-394

1994

Link zum Volltext
IEEE_Xplore

A 0.8 W HDTV video processor with simultaneous decoding of two MPEG2 MP@HL streams and capable of 30 frames/s reverse playback

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Vol.1, p.372-474 vol.1

2002

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IEEE_Xplore

A 0.8W HDTV video processor with simultaneous decoding of two MPEG2 MP@HL streams and capable of 30frames/s reverse playback

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Vol.2, p.300-514

2002

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IEEE_Xplore

001. 水銀の尿中排泄量の評価

産業医学, 1968/04/20, Vol.10(4), pp.201

1968

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003 Aging alteration of skin T cells is different from that of blood T cells

Journal of investigative dermatology, 2019-09, Vol.139 (9), p.S215-S215

2019

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005 Respiratory activity in psoriatic circulating T cells predicts the efficacy of apremilast

Journal of investigative dermatology, 2020-07, Vol.140 (7), p.S1-S1

2020

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0052: Practice Patterns for the Postoperative Management of Endometrial Cancer: a Survey of the Japanese Gynecologic Oncology Group (JGOG)

International journal of gynecological cancer, 2006-10, Vol.16 (Suppl 3), p.614-614

2006

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A 0.1e- vertical FPN 4.7e- read noise 71dB DR CMOS image sensor with 13b column-parallel single-ended cyclic ADCs

A 0.2-/spl mu/m bipolar-CMOS technology on bonded SOI with copper metallization for ultra high-speed processors

0.29-/spl mu/m/sup 2/ trench cell technologies for 1G-bit DRAMs with open/folded-bit-line layout and selective growth technique

A 0.35 /spl mu/m ECL-CMOS process technology on SOI for 1 ns mega-bits SRAMs with 40 ps gate array

A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW

0.5- mu m 2 M-transistor BiPNMOS channelless gate array

0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file

0.5-mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache andten-port register file

0.5 mu m BiCMOS standard-cell macros including 0.5 W 3 ns register file and 0.6 W 5 ns 32 kB cache

0.5/spl mu/m 2M-transistor BipnMOS Channelless Gate Array

A 0.5 V 200 MHz 1-stage 32 b ALU using a body bias controlled SOI pass-gate logic

0.5 V SOI CMOS pass-gate logic

0.5-μm 2M-transistor BiPNMOS channelless gate array

0.5-μm 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file : Memory and logic

A 0.5 μm BiCMOS channelless gate array

0.6 /spl mu/m BiCMOS based 15 and 25 V LDMOS for analog applications

A 0.602 /spl mu/m/sup 2/ nestled 'Chain' cell structure formed by one mask etching process for 64 Mbit FeRAM

A 0.602 um2 nestled chain cell structure formed by one mask etching process for 64 mbit FeRAM

A 0.7-mW/2-GHz dual modulus prescaler IC

A 0.8 W HDTV video processor with simultaneous decoding of two MPEG2 MP@HL streams and capable of 30 frames/s reverse playback

A 0.8W HDTV video processor with simultaneous decoding of two MPEG2 MP@HL streams and capable of 30frames/s reverse playback

001. 水銀の尿中排泄量の評価

003 Aging alteration of skin T cells is different from that of blood T cells

005 Respiratory activity in psoriatic circulating T cells predicts the efficacy of apremilast

0052: Practice Patterns for the Postoperative Management of Endometrial Cancer: a Survey of the Japanese Gynecologic Oncology Group (JGOG)

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