UB Paderborn / Katalog / Suche / in CDI

Design of High-Speed and Power-Efficient Ternary Prefix Adders Using CNFETs

IEEE transactions on nanotechnology, 2018-07, Vol.17 (4), p.772-782

2018

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Design Methodologies for Ternary Logic Circuits

2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), 2018, p.192-197

2018

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Design of CNFET-based Ternary Conditional Sum Adders using Binary Carry Propagation

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

Vudadha, Chetan

2024

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Novel Design Methodologies for CNFET-Based Ternary Sequential Logic Circuits

IEEE transactions on nanotechnology, 2022, Vol.21, p.289-298

2022

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Design of CNTFET-Based Ternary ALU Using 2:1 Multiplexer Based Approach

IEEE transactions on nanotechnology, 2020, Vol.19, p.661-671

2020

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Design of a Ternary Logic Processor Using CNTFET Technology

Circuits, systems, and signal processing, 2024-06, Vol.43 (9), p.5809-5833

2024

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Synthesis of Ternary Logic Circuits Using 2:1 Multiplexers

IEEE transactions on circuits and systems. I, Regular papers, 2018-12, Vol.65 (12), p.4313-4325

2018

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A Novel Low Power Ternary Multiplier Design using CNFETs

2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID), 2020, p.25-30

2020

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An ESOP Based Cube Decomposition Technique for Reversible Circuits

Reversible Computation, p.127-140

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FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, p.1-5

2020

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Encoder-Based Optimization of CNFET-Based Ternary Logic Circuits

IEEE transactions on nanotechnology, 2018-03, Vol.17 (2), p.299-310

2018

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Optimization of Reversible Circuits Using Gate Pair Classification

SN computer science, 2022, Vol.3 (1), p.40, Article 40

2022

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Power efficient designs of CNTFET-based ternary SRAM

Microelectronics, 2023-09, Vol.139, p.105884, Article 105884

2023

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Optimizing the Reversible Circuits Using Complementary Control Line Transformation

Reversible Computation, p.111-126

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Design of CNFET-based Low-Power Ternary Sequential Logic circuits

2021 IEEE 21st International Conference on Nanotechnology (NANO), 2021, p.169-172

2021

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Design of CNTFET-based Ternary Logic circuits using Low power Encoder

2022 IEEE International Symposium on Smart Electronic Systems (iSES), 2022, p.142-147

2022

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PDCCH Signaling Constrained Mean SNR-Based Resource Allocation for Semi-Persistent Scheduler

2023 IEEE 16th Malaysia International Conference on Communication (MICC), 2023, p.113-118

2023

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An Optimized Design of Reversible Quantum Comparator

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014, p.557-562

2014

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Energy efficient design of CNFET-based multi-digit ternary adders

Microelectronics, 2018-05, Vol.75, p.75-86

2018

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An Approximate Full-Adder to Eliminate Carry Propagation in Lower Significant Stage of a Multi-Digit Adder

2023 International Conference on Computer, Electronics & Electrical Engineering & their Applications (IC2E3), 2023, p.1-6

2023

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Evaluation of x86 and ARM architectures using compute-intensive workloads

2022 IEEE International Symposium on Smart Electronic Systems (iSES), 2022, p.586-589

2022

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Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs

2012 25th International Conference on VLSI Design, 2012, p.280-285

2012

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Design of Area Optimised, Energy Efficient Quaternary Circuits Using CNTFETs

2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), 2019, p.280-283

2019

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Design of Ternary Logic Circuits Using CNFETs

Nanoscale Devices, 2019, p.225-253

1, 2019

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An Efficient Design Methodology for CNFET Based Ternary Logic Circuits

2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), 2016, p.278-283

2016

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Design of High-Speed and Power-Efficient Ternary Prefix Adders Using CNFETs

Design Methodologies for Ternary Logic Circuits

Design of CNFET-based Ternary Conditional Sum Adders using Binary Carry Propagation

Novel Design Methodologies for CNFET-Based Ternary Sequential Logic Circuits

Design of CNTFET-Based Ternary ALU Using 2:1 Multiplexer Based Approach

Design of a Ternary Logic Processor Using CNTFET Technology

Synthesis of Ternary Logic Circuits Using 2:1 Multiplexers

A Novel Low Power Ternary Multiplier Design using CNFETs

An ESOP Based Cube Decomposition Technique for Reversible Circuits

FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design

Encoder-Based Optimization of CNFET-Based Ternary Logic Circuits

Optimization of Reversible Circuits Using Gate Pair Classification

Power efficient designs of CNTFET-based ternary SRAM

Optimizing the Reversible Circuits Using Complementary Control Line Transformation

Design of CNFET-based Low-Power Ternary Sequential Logic circuits

Design of CNTFET-based Ternary Logic circuits using Low power Encoder

PDCCH Signaling Constrained Mean SNR-Based Resource Allocation for Semi-Persistent Scheduler

An Optimized Design of Reversible Quantum Comparator

Energy efficient design of CNFET-based multi-digit ternary adders

An Approximate Full-Adder to Eliminate Carry Propagation in Lower Significant Stage of a Multi-Digit Adder

Evaluation of x86 and ARM architectures using compute-intensive workloads

Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs

Design of Area Optimised, Energy Efficient Quaternary Circuits Using CNTFETs

Design of Ternary Logic Circuits Using CNFETs

An Efficient Design Methodology for CNFET Based Ternary Logic Circuits

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