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Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm

IEEE electron device letters, 2012-11, Vol.33 (11), p.1526-1528

2012

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A Review of Low Temperature Process Modules Leading Up to the First (≤500 °C) Planar FDSOI CMOS Devices for 3-D Sequential Integration

IEEE transactions on electron devices, 2021-07, Vol.68 (7), p.3142-3148

2021

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Top-down fabrication and electrical characterization of Si and SiGe nanowires for advanced CMOS technologies

Semiconductor science and technology, 2019-07, Vol.34 (7), p.74001

2019

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7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing

2020 IEEE Symposium on VLSI Technology, 2020, p.1-2

2020

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Single-mode waveguides for GRAVITY

Astronomy and astrophysics (Berlin), 2018-06, Vol.614

2018

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Low defect InGaAs quantum well selectively grown by metal organic chemical vapor deposition on Si(100) 300 mm wafers for next generation non planar devices

Applied physics letters, 2014-06, Vol.104 (26)

2014

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Three dimensional on 300 mm wafer scale nano imprint lithography processes

Microelectronic engineering, 2013-10, Vol.110, p.198-203

2013

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Three dimensional on 300mm wafer scale nano imprint lithography processes

Microelectronic engineering, 2013-10, Vol.110, p.198-203

2013

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All-Operation-Regime Characterization and Modeling of Drain Current Variability in Junctionless and Inversion-Mode FDSOI Transistors

2020 IEEE Symposium on VLSI Technology, 2020, p.1-2

2020

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First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers

2016 IEEE Symposium on VLSI Technology, 2016, p.1-2

2016

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Scaling of Trigate nanowire (NW) MOSFETs to sub-7 nm width: 300 K transition to Single Electron Transistor

Solid-state electronics, 2013-06, Vol.84, p.179-184

2013

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Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs

Solid-state electronics, 2013-06, Vol.84, p.46-52

2013

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Bonded planar double-metal-gate NMOS transistors down to 10 nm

IEEE electron device letters, 2005-05, Vol.26 (5), p.317-319

2005

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First Demonstration of Low Temperature (≤500°C) CMOS Devices Featuring Functional RO and SRAM Bitcells toward 3D VLSI Integration

2020 IEEE Symposium on VLSI Technology, 2020, p.1-2

2020

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Performance and design considerations for gate-all-around stacked-NanoWires FETs

2017 IEEE International Electron Devices Meeting (IEDM), 2017, p.29.2.1-29.2.4

2017

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High-Density 3D Monolithically Integrated Multiple 1T1R Multi-Level-Cell for Neural Networks

2020 IEEE International Electron Devices Meeting (IEDM), 2020, p.36.5.1-36.5.4

2020

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3D nanowire gate-all-around transistors: Specific integration and electrical features

Solid-state electronics, 2008-04, Vol.52 (4), p.519-525

2008

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Ultra-dense silicon nanowires: A technology, transport and interfaces challenges insight (invited)

Microelectronic engineering, 2011-07, Vol.88 (7), p.1198-1202

2011

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High mobility CMOS: First demonstration of planar GeOI p-FETs with SOI n-FETs

Solid-state electronics, 2011-05, Vol.59 (1), p.2-7

2011

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Self-Aligned Planar Double-Gate MOSFETs by Bonding for 22-nm Node, With Metal Gates, High- \kappa Dielectrics, and Metallic Source/Drain

IEEE electron device letters, 2009-07, Vol.30 (7), p.748-750

2009

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Hybrid high resolution lithography (e-beam/deep ultraviolet) and etch process for the fabrication of stacked nanowire metal oxide semiconductor field effect transistors

Journal of vacuum science & technology. B, Microelectronics and nanometer structures processing, measurement and phenomena, 2008-11, Vol.26 (6), p.2583-2586

2008

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Single-mode waveguides for GRAVITY: I. The cryogenic 4-telescope integrated optics beam combiner

Astronomy and astrophysics (Berlin), 2018-06, Vol.614, p.A70

2018

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Si/Si0.7Ge0.3 A2RAM nanowires fabrication and characterization for 1T-DRAM applications

Solid-state electronics, 2022-07, Vol.193, p.108294, Article 108294

2022

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Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012, p.121-124

2012

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Single dopant impact on electrical characteristics of SOI NMOSFETs with effective length down to 10nm

2010 Symposium on VLSI Technology, 2010, p.193-194

2010

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Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm

A Review of Low Temperature Process Modules Leading Up to the First (≤500 °C) Planar FDSOI CMOS Devices for 3-D Sequential Integration

Top-down fabrication and electrical characterization of Si and SiGe nanowires for advanced CMOS technologies

7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing

Single-mode waveguides for GRAVITY

Low defect InGaAs quantum well selectively grown by metal organic chemical vapor deposition on Si(100) 300 mm wafers for next generation non planar devices

Three dimensional on 300 mm wafer scale nano imprint lithography processes

Three dimensional on 300mm wafer scale nano imprint lithography processes

All-Operation-Regime Characterization and Modeling of Drain Current Variability in Junctionless and Inversion-Mode FDSOI Transistors

First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers

Scaling of Trigate nanowire (NW) MOSFETs to sub-7 nm width: 300 K transition to Single Electron Transistor

Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs

Bonded planar double-metal-gate NMOS transistors down to 10 nm

First Demonstration of Low Temperature (≤500°C) CMOS Devices Featuring Functional RO and SRAM Bitcells toward 3D VLSI Integration

Performance and design considerations for gate-all-around stacked-NanoWires FETs

High-Density 3D Monolithically Integrated Multiple 1T1R Multi-Level-Cell for Neural Networks

3D nanowire gate-all-around transistors: Specific integration and electrical features

Ultra-dense silicon nanowires: A technology, transport and interfaces challenges insight (invited)

High mobility CMOS: First demonstration of planar GeOI p-FETs with SOI n-FETs

Self-Aligned Planar Double-Gate MOSFETs by Bonding for 22-nm Node, With Metal Gates, High- \kappa Dielectrics, and Metallic Source/Drain

Hybrid high resolution lithography (e-beam/deep ultraviolet) and etch process for the fabrication of stacked nanowire metal oxide semiconductor field effect transistors

Single-mode waveguides for GRAVITY: I. The cryogenic 4-telescope integrated optics beam combiner

Si/Si0.7Ge0.3 A2RAM nanowires fabrication and characterization for 1T-DRAM applications

Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities

Single dopant impact on electrical characteristics of SOI NMOSFETs with effective length down to 10nm

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