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Power-Aware Computer Systems: First International Workshop, PACS 2000 Cambridge, MA, USA, November 12, 2000 Revised Papers

1, 2001

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Power-Aware Computer Systems: Second International Workshop, PACS 2002 Cambridge, MA, USA, February 2, 2002, Revised Papers

1, 2003

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Software-programmable continuous-flow multi-purpose lab-on-a-chip

Microfluidics and nanofluidics, 2013-11, Vol.15 (5), p.647-659

2013

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Newton: A DRAM-maker's Accelerator-in-Memory (AiM) Architecture for Machine Learning

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2020, p.372-385

2020

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Dart: Divide and Specialize for Fast Response to Congestion in RDMA-Based Datacenter Networks

IEEE/ACM transactions on networking, 2020-02, Vol.28 (1), p.322-335

2020

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MapReduce with communication overlap (MaRCO)

Journal of parallel and distributed computing, 2013-05, Vol.73 (5), p.608-620

2013

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Karma: Cost-Effective Geo-Replicated Cloud Storage with Dynamic Enforcement of Causal Consistency

IEEE transactions on cloud computing, 2021-01, Vol.9 (1), p.197-211

2021

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DCG: deterministic clock-gating for low-power microprocessor design

IEEE transactions on very large scale integration (VLSI) systems, 2004-03, Vol.12 (3), p.245-254

2004

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Reducing set-associative cache energy via way-prediction and selective direct-mapping

Proceedings of the annual International Symposium on Microarchitecture, 2001, p.54-65

2001

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Optimizing Replication, Communication, and Capacity Allocation in CMPs

ACM SIGARCH Computer Architecture News, 2005, Vol.33 (2), p.357-368

2005

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Reducing leakage in a high-performance deep-submicron instruction cache

IEEE transactions on very large scale integration (VLSI) systems, 2001-02, Vol.9 (1), p.77-89

2001

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Optimizing Replication, Communication, and Capacity Allocation in CMPs

32nd International Symposium on Computer Architecture (ISCA'05), 2005, p.357-368

2005

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Power-Aware Computer Systems: 4th International Workshop, PACS 2004, Portland, or, USA, December 5, 2004, Revised Selected Papers

1, 2005

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Power-Aware Computer Systems: Third International Workshop, PACS 2003, San Diego, CA, USA, December 1, 2003, Revised Papers

1, 2004

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A program transformation and architecture support for quantum uncomputation

ASPLOS XII : Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems, October 21-25, 2006, San Jose, California, USA, 2006, Vol.40 (5), p.252-263

2006

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Exploiting reference idempotency to reduce speculative storage overflow

ACM transactions on programming languages and systems, 2006-09, Vol.28 (5), p.942-965

2006

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Rescue: A Microarchitecture for Testability and Defect Tolerance

32nd International Symposium on Computer Architecture (ISCA'05), 2005, p.160-171

2005

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Reactive-associative caches

Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques, 2001, p.49-60

2001

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Exploiting Resonant Behavior to Reduce Inductive Noise

International Symposium on Computer Architecture: Proceedings of the 31st annual international symposium on Computer architecture : Munchen, Germany; 19-23 June 2004, 2004, p.288-288

2004

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SmashGuard: A Hardware Solution to Prevent Security Attacks on the Function Return Address

IEEE transactions on computers, 2006-10, Vol.55 (10), p.1271-1285

2006

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Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?

Architecture of Computing Systems - ARCS 2006, 2006, p.232-251

2006

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Multiscalar processors

International Symposium on Computer Architecture: Proceedings of the 22nd annual international symposium on Computer architecture; 22-24 June 1995, 1995, p.414-425

1995

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FaultHound: value-locality-based soft-fault tolerance

2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA), 2015, p.668-681

2015

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Task selection for a multiscalar processor

Proceedings of the annual International Symposium on Microarchitecture, 1998, p.81-92

1998

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SparTen: A Sparse Tensor Accelerator for Convolutional Neural Networks

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019, p.151-165

2019

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Power-Aware Computer Systems: First International Workshop, PACS 2000 Cambridge, MA, USA, November 12, 2000 Revised Papers

Power-Aware Computer Systems: Second International Workshop, PACS 2002 Cambridge, MA, USA, February 2, 2002, Revised Papers

Software-programmable continuous-flow multi-purpose lab-on-a-chip

Newton: A DRAM-maker's Accelerator-in-Memory (AiM) Architecture for Machine Learning

Dart: Divide and Specialize for Fast Response to Congestion in RDMA-Based Datacenter Networks

MapReduce with communication overlap (MaRCO)

Karma: Cost-Effective Geo-Replicated Cloud Storage with Dynamic Enforcement of Causal Consistency

DCG: deterministic clock-gating for low-power microprocessor design

Reducing set-associative cache energy via way-prediction and selective direct-mapping

Optimizing Replication, Communication, and Capacity Allocation in CMPs

Reducing leakage in a high-performance deep-submicron instruction cache

Optimizing Replication, Communication, and Capacity Allocation in CMPs

Power-Aware Computer Systems: 4th International Workshop, PACS 2004, Portland, or, USA, December 5, 2004, Revised Selected Papers

Power-Aware Computer Systems: Third International Workshop, PACS 2003, San Diego, CA, USA, December 1, 2003, Revised Papers

A program transformation and architecture support for quantum uncomputation

Exploiting reference idempotency to reduce speculative storage overflow

Rescue: A Microarchitecture for Testability and Defect Tolerance

Reactive-associative caches

Exploiting Resonant Behavior to Reduce Inductive Noise

SmashGuard: A Hardware Solution to Prevent Security Attacks on the Function Return Address

Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?

Multiscalar processors

FaultHound: value-locality-based soft-fault tolerance

Task selection for a multiscalar processor

SparTen: A Sparse Tensor Accelerator for Convolutional Neural Networks

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