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Modeling the Operation of Charge Trap Flash Memory-Part I: The Importance of Carrier Energy Relaxation

IEEE transactions on electron devices, 2024-01, Vol.71 (1), p.547-553

2024

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InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature

Applied physics letters, 2016-12, Vol.109 (24)

2016

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Large Variation in Temperature Dependence of Band-to-Band Tunneling Current in Tunnel Devices

IEEE electron device letters, 2019-11, Vol.40 (11), p.1864-1867

2019

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Analysis of BTI in 300 mm integrated dual-gate WS2 FETs

2022 Device Research Conference (DRC), 2022, p.1-2

2022

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Impact of gate stack processing on the hysteresis of 300 mm integrated WS2 FETs

2023 IEEE International Reliability Physics Symposium (IRPS), 2023, p.1-6

2023

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3D TCAD Model for Poly-Si Channel Current and Variability in Vertical NAND Flash Memory

2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2019, p.1-4

2019

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Application of Single Pulse Dynamics to Model Program and Erase Cycling-Induced Defects in the Tunnel Oxide of Charge-Trapping Devices

2019 IEEE International Integrated Reliability Workshop (IIRW), 2019, p.1-3

2019

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An inner gate as enabler for vertical pitch scaling in macaroni channel gate-all-around 3-D NAND flash memory

Solid-state electronics, 2023-01, Vol.199, p.108498, Article 108498

2023

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Introducing 2D-FETs in Device Scaling Roadmap using DTCO

2020 IEEE International Electron Devices Meeting (IEDM), 2020, p.22.5.1-22.5.4

2020

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Quantum Mechanical Performance Predictions of p-n-i-n Versus Pocketed Line Tunnel Field-Effect Transistors

IEEE transactions on electron devices, 2013-07, Vol.60 (7), p.2128-2134

2013

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Understanding the ISPP Slope in Charge Trap Flash Memory and its Impact on 3-D NAND Scaling

2021 IEEE International Electron Devices Meeting (IEDM), 2021, p.1-4

2021

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Enabling 3D NAND Trench Cells for Scaled Flash Memories

2023 IEEE International Memory Workshop (IMW), 2023, p.1-4

2023

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At the Extreme of 3D-NAND Scaling: 25 nm Z-Pitch with 10 nm Word Line Cells

2022 IEEE International Memory Workshop (IMW), 2022, p.1-4

2022

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A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics

2021 IEEE International Memory Workshop (IMW), 2021, p.1-4

2021

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Program charge interference and mitigation in vertically scaled single and multiple-channel 3D NAND flash memory

2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2021, p.268-271

2021

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Impact of Mechanical Stress on the Electrical Performance of 3D NAND

2019 IEEE International Reliability Physics Symposium (IRPS), 2019, p.1-5

2019

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Liquid Memory and the Future of Data Storage

2022 IEEE International Memory Workshop (IMW), 2022, p.1-4

2022

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Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors

2016 46th European Solid-State Device Research Conference (ESSDERC), 2016, p.412-415

2016

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Quantitative 3-D Model to Explain Large Single Trap Charge Variability in Vertical NAND Memory

2019 IEEE International Electron Devices Meeting (IEDM), 2019, p.32.1.1-32.1.4

2019

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Can p-channel tunnel field-effect transistors perform as good as n-channel?

Applied physics letters, 2014-07, Vol.105 (4)

2014

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2D materials: roadmap to CMOS integration

2018 IEEE International Electron Devices Meeting (IEDM), 2018, p.22.1.1-22.1.4

2018

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15-band spectral envelope function formalism applied to broken gap tunnel field-effect transistors

2015 International Workshop on Computational Electronics (IWCE), 2015, p.1-4

2015

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Beyond-Si materials and devices for more Moore and more than Moore applications

2016 International Conference on IC Design and Technology (ICICDT), 2016, p.1-5

2016

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Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab

2020 IEEE International Electron Devices Meeting (IEDM), 2020, p.40.2.1-40.2.4

2020

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Band-to-band tunneling in MOS-capacitors for rapid tunnel-FET characterization

72nd Device Research Conference, 2014, p.63-64

2014

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Modeling the Operation of Charge Trap Flash Memory-Part I: The Importance of Carrier Energy Relaxation

InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature

Large Variation in Temperature Dependence of Band-to-Band Tunneling Current in Tunnel Devices

Analysis of BTI in 300 mm integrated dual-gate WS2 FETs

Impact of gate stack processing on the hysteresis of 300 mm integrated WS2 FETs

3D TCAD Model for Poly-Si Channel Current and Variability in Vertical NAND Flash Memory

Application of Single Pulse Dynamics to Model Program and Erase Cycling-Induced Defects in the Tunnel Oxide of Charge-Trapping Devices

An inner gate as enabler for vertical pitch scaling in macaroni channel gate-all-around 3-D NAND flash memory

Introducing 2D-FETs in Device Scaling Roadmap using DTCO

Quantum Mechanical Performance Predictions of p-n-i-n Versus Pocketed Line Tunnel Field-Effect Transistors

Understanding the ISPP Slope in Charge Trap Flash Memory and its Impact on 3-D NAND Scaling

Enabling 3D NAND Trench Cells for Scaled Flash Memories

At the Extreme of 3D-NAND Scaling: 25 nm Z-Pitch with 10 nm Word Line Cells

A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics

Program charge interference and mitigation in vertically scaled single and multiple-channel 3D NAND flash memory

Impact of Mechanical Stress on the Electrical Performance of 3D NAND

Liquid Memory and the Future of Data Storage

Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors

Quantitative 3-D Model to Explain Large Single Trap Charge Variability in Vertical NAND Memory

Can p-channel tunnel field-effect transistors perform as good as n-channel?

2D materials: roadmap to CMOS integration

15-band spectral envelope function formalism applied to broken gap tunnel field-effect transistors

Beyond-Si materials and devices for more Moore and more than Moore applications

Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab

Band-to-band tunneling in MOS-capacitors for rapid tunnel-FET characterization

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