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A novel approach for the design of low-power pipelined synchronous systems operating in double–edge of the clock
Microelectronics, 2021-01, Vol.107, p.104947, Article 104947
2021
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CUBES phase a design overview: The Cassegrain U-Band efficient spectrograph for the very large telescope
Experimental astronomy, 2023-02, Vol.55 (1), p.241-265
2023
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CUBES phase a design overview
Experimental astronomy, 2023-01, Vol.55 (1), p.241-265
2023
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Synthesis of QDI Combinational Circuits Based at the New Factorized DIMS
2023 IEEE Seventh Ecuador Technical Chapters Meeting (ECTM), 2023, p.1-6
2023
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Interfacing Synchronous Modules to Multi-Clock Synchronous Digital Systems Implemented in FPGA
2023 IEEE Seventh Ecuador Technical Chapters Meeting (ECTM), 2023, p.1-6
2023
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Synthesis of QDI Combinational Circuits using Null Convention Logic Based on Basic Gates
Advances in Science, Technology and Engineering Systems Journal, 2018-08, Vol.3 (4), p.308-317
2018
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Fault-Tolerant Finite State Machine Quasi Delay Insensitive in Commercial FPGA Devices
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS), 2022, p.1-4
2022
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Synthesis of Quasi Delay Insensitive Asynchronous State Machines from Synchronous Specifications
2021 IEEE XXVIII International Conference on Electronics, Electrical Engineering and Computing (INTERCON), 2021, p.1-4
2021
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Fault-Tolerant Quasi Delay Insensitive Combinational Circuits in Commercial FPGA Devices
2021 IEEE 22nd Latin American Test Symposium (LATS), 2021, p.1-6
2021
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Synthesis of QDI AFSMs from XBM specifications
2018 2nd Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA), 2018, p.1-4
2018
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A Tools Flow for Extended Burst-Mode State Machines Design with Enhanced Robustness
2020 IEEE XXVII International Conference on Electronics, Electrical Engineering and Computing (INTERCON), 2020, p.1-4
2020
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Implementation of DES Algorithm in New Non-Synchronous Architecture Aiming DPA Robustness
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.228-229
2019
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A novel Κ convention logic (NCL) gates architecture based on basic gates
2017 IEEE XXIV International Conference on Electronics, Electrical Engineering and Computing (INTERCON), 2017, p.1-4
2017
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State assignment of direct output synchronous FSMs using genetic algorithm
2017 IEEE XXIV International Conference on Electronics, Electrical Engineering and Computing (INTERCON), 2017, p.1-4
2017
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Robust architecture for locally-clocked extended burst-mode circuits without timing assumption
2017 IEEE XXIV International Conference on Electronics, Electrical Engineering and Computing (INTERCON), 2017, p.1-4
2017
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Software-defined radio design based on GALS architecture for FPGAs
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design: Chip on the Mountains, 2017, p.1-6
2017
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A High Performance Implementation of Quasi Delay Insensitive Booleans Functions
2019 IEEE XXVI International Conference on Electronics, Electrical Engineering and Computing (INTERCON), 2019, p.1-4
2019
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A Design Flow for Synthesis of Quasi Delay Insensitive Combinational Circuits
2020 IEEE XXVII International Conference on Electronics, Electrical Engineering and Computing (INTERCON), 2020, p.1-4
2020
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Software-Defined Radio design based on GALS architecture for FPGAs
2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI), 2016, p.1-6
2016
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An Implementation of Extended Burst-Mode Specifications as Quasi Delay Insensitive State Machines
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), 2019, p.177-180
2019
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A Novel Architecture for Implementation of Quasi Delay Insensitive Finite State Machines
2018 IEEE XXV International Conference on Electronics, Electrical Engineering and Computing (INTERCON), 2018, p.1-4
2018
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Synthesis of passive filter using object oriented genetic algorithm
2014 26th International Conference on Microelectronics (ICM), 2014, p.72-75
2014
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